Sun Microsystems SunSwift SPARCserver 1000, Руководство по обслуживанию

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Functional Description B-3
B
Figure B-3 Detailed Block Diagram
B.3 Arbitration System
The SPARCserver 1000 supports a large number of devices that demand
ownership of system resources, including exclusive access to the system
backplane address and data bus. To prevent conflicts over access to resources,
SPARCserver 1000 has a two-tier arbitration system; one tier monitors the
boards; the other tier, which is higher, monitors the overall system.
Each system board has a board arbiter (BARB). The function of the BARB is to
determine which device (bus watcher (BW), memory queue handler (MQH), or
I/O cache (IOC)) is next in line to access the XDBus.
DRAM
group
I/O
Cache
(IOC)
Memory
control
(MQH)
SBus
Intf.
(SBI)
Bus
watcher
(BW)
BIC
and
BARB
Data
Addr
SBus
SPARC module SPARC module
LEDS JTAG Control
SRAM
UARTs EPROM
BBC2
BootBus
CPU
Cache
control
XBus
XBus
CPU
High
speed
cache
plus
parity
Cache
control
High
speed
cache
plus
parity
TODC/NVRAM
Bus
watcher
(BW)
DRAM
group
Slot 3
On-board
ethernet
and SCSI
Slot 2
Slot 1
Page
table
Data
Addr
XBus