Sun Microsystems Netra CP3060, Руководство пользователя

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Chapter 5 Hardware and Functional Descriptions 5-9
5.1.2.3 Serial Presence Detect
The Sun Netra CP3060 blade server supports autoconfiguration using serial presence
detect (SPD). The DIMMs have small EEPROM devices that store their configuration
data according to the SPD format. MPC/vBSC reads this data via the I
2
C
management bus, and writes the data into the OpenBoot PROM.
A 128-byte region of the SPD EEPROM is available for user data storage, allowing a
limited form of FRU information to be implemented for the DIMMs.
5.1.3 System JBus
The JBus is the main interconnect for the core of every UltraSPARC T1-based system.
The JBus is a memory-coherent interconnect joining the UltraSPARC T1 processor to
the JBus-to-PCI-E bridge.
JBus provides a memory-coherent 128-bit shared address/data path between each of
the JBus resident devices. The JBus uses the Dynamic Termination Logic (DTL)
signaling environment created initially for the UltraSPARC III, and is a globally
clocked bus designed to run with a maximum clock frequency of 200 MHz. Memory
coherence is maintained through the use of a snooping
Modified-Owned-Exclusive-Invalid (MOESI) cache protocol, wherein all JBus agents
must snoop their own cache hierarchies on every transaction that goes across the
JBus interconnect.
5.1.3.1 JBus RAS Features
JBus provides parity protection on all address and data transfers. One set of parity
signals provides parity protection over the multiplexed address/data bus, and
another provides parity over the control signals. Address and control parity errors
cause a fatal reset, while data parity errors are treated on a per-instance basis,
depending on the producer and consumer of the data.
5.1.4 I/O Subsystem
The I/O subsystem implements the JBus and PCI-E fabrics, including the
JBus-to-PCI-E bridge, one PCI-E switch, one AMC slot, two Intel PCI-E dual gigabit
Ethernet chips, a PC-E UliM1575 Southbridge chip, and miscellaneous logic.