Sun Microsystems Netra CP3060, Руководство пользователя

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5-4 Netra CP3060 Board User’s Guide • April 2009
5.1.1 UltraSPARC T1 Processor
This section provides a brief description of the salient features of the UltraSPARC T1
processor, its package, and its socket.
5.1.1.1 Overview
The UltraSPARC T1 multicore processor is the basis of the Sun Netra CP3060 blade
server. The UltraSPARC T1 processor is based on chip multithreading (CMT)
technology that is optimized for highly threaded transactional processing. The
UltraSPARC T1 processor improves throughput while using less power and
dissipating less heat than conventional processor designs.
Depending on the model purchased, the processor has four, six, or eight UltraSPARC
cores. Each core equates to a 64-bit execution pipeline capable of running four
threads. The result is that the 8-core processor handles up to 32 active threads
concurrently.
Additional processor components, such as L1 cache, L2 cache, memory access
crossbar, DDR2 memory controllers, and a JBus I/O interface have been carefully
tuned for optimal performance. See
FIGURE 5-2
.
The CPU is a high-performance, highly integrated superscaler UltraSPARC T1
processor implementing the 64-bit SPARC-V9 RISC architecture. It contains a
128-Kbyte instruction cache and 64-Kbyte data cache. The chip has an inbuilt
3-Mbyte L2 cache that uses a 32-byte cache line.