Sun Microsystems Cobalt LX50, Руководство пользователя

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Power-On Self Test (POST)
User Guide—Sun Cobalt LX50 Server 6-13
08h G Off Off Off Verify CMOS checksum.
07h Off G G G Read microcode updates from BIOS ROM.
07h Off G G G Initializing the processors. Set up processor registers. Select least featured
processor as the BSP.
0Bh G Off G G Hook before the keyboard BAT command is issued.
0Ch G G Off Off Keyboard Controller Test: the keyboard controller input buffer is free.
Next, issuing the BAT command to the keyboard controller
0Eh G G G Off Init after keyboard test: the keyboard controller BAT command result has
been verified. Next, performing any necessary initialization after the
keyboard controller BAT command test.
0Fh G G G G Write Command Byte 8042: the initialization after the keyboard controller
BAT command test is done. The keyboard command byte will be written
next.
10h Off Off Off R Keyboard Init: the keyboard controller command byte is written. Next,
issuing the pin 23 and 24 blocking and unblocking commands
10h Off Off Off R Disable and initialize 8259.
11h Off Off Off A Detect configuration mode, such as CMOS clear.
13h Off Off G A Chipset initialization before CMOS initialization.
19h G Off Off A Init System Timer: the 8254 timer test is over. Starting the memory refresh
test next
1Ah G Off G R Check Refresh Toggle: the memory refresh line is toggling. Checking the
15 second on/off time next.
23h Off Off A G Setup Interrupt Vectors: reading the 8042 input port and disabling the
MEGAKEY Green PC feature next. Making the BIOS code segment
writable and performing any necessary configuration before initializing
the interrupt vectors.
24h Off G R Off Before Vector: configuration is required before interrupt vector
initialization has completed. Interrupt vector initialization is about to
begin.
25h Off G R G Init interrupt Vectors: interrupt vector initialization is done.
F2h R R A R Initialize SMM handler. Initialize USB emulation.
F5h R A R A Validate NVRAM areas. Restore from backup if corrupted.
12h Off Off G R Load defaults in CMOS RAM if bad checksum or CMOS clear jumper is
detected.
12h Off Off G R Initializing APP CMOS RAM for appliance servers only.
12h Off Off G R Check point after CMOS initialized.
27h Off G A G Validate date and time in RTC.
F4h R A R R Load micro code to all CPUs.
F6h R A A R Scan SMBIOS GPNV areas.
Table 18. POST LEDs Code Table (Port 80h Codes) (Continued)
POST
Code
Diagnostic LED Decoder
(G = green, R = red, A = amber)
Description