Sony PEGA-CC5, Руководство по обслуживанию

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50
PEGA-CC5
• MAIN BOARD IC14 TC200G58EFG-0007 (ASIC)
Pin No. Pin Name I/O Description
1 T2 — Not used
2 VDD — Power supply terminal (+3.3V)
3 VSS — Ground terminal
4 FM_ON O Power on/off control signal output for the FM transmitter
5 FMCE O Chip enable signal output to the FM transmitter
6 FMCLK O Serial data transfer clock signal output to the FM transmitter
7 FMDATA O Serial data output to the FM transmitter
8 FMMUTE O Muting on/off control signal output to the FM transmitter
9 SPMUTE O Muting on/off control signal output to the speaker amplifier
10 CMUTE O Muting on/off control signal output for the line output
11 SBUSMUTE O Muting on/off control signal output for the SONY bus Not used
12 VSS — Ground terminal
13 CLIE_POWER O Power control signal output for a CLIE Not used
14 CHARGE O Charge on/off control signal output for a CLIE
15 HOTSYNC O HOT-SYNC signal output to a CLIE
16 UNREG_OUT I Cradle detection input of a CLIE
17 VSS — Ground terminal
18 VDD — Power supply terminal (+3.3V)
19 to 25 BA0 to BA6 I Address signal input from the CPU
26 VDD — Power supply terminal (+3.3V)
27 VSS — Ground terminal
28 to 33 BA7 to BA12 I Address signal input from the CPU
34 ALE I Address latch signal (upper byte) input from the CPU
35 VSS — Ground terminal
36 VDD — Power supply terminal (+3.3V)
37 VSS — Ground terminal
38 to 43 BD0 to BD5 I/O Two-way data bus with the CPU and flash memory
44 VSS — Ground terminal
45 to 50 BD6 to BD11 I/O Two-way data bus with the CPU and flash memory
51 VSS — Ground terminal
52 VDD — Power supply terminal (+3.3V)
53, 54 BD12, BD13 I/O Two-way data bus with the CPU and flash memory
55 VSS — Ground terminal
56, 57 BD14, BD15 I/O Two-way data bus with the CPU and flash memory
58 RD I Data read enable signal input from the CPU
59 WR I Write strobe signal input from the CPU
60 CS0 I Chip select signal input from the CPU
61 CS1 I Chip select signal input from the CPU
62 VSS — Ground terminal
63 DCLK I Clock signal input from the CPU
64 VSS — Ground terminal
65 VDD — Power supply terminal (+3.3V)
66 to 70 INT0 to INT4 O Interrupt request signal output to the CPU
71 CLK32K O Not used
72 VSS — Ground terminal