45
PEGA-CC5
Pin No.
Pin Name
I/O
Description
49 to 52 GPIO0 to GPIO3
I/O
Not used
53
NC6
—
Not used
54
DVSS1
—
Ground terminal
55
RST
I
System reset signal input from the CPU
56
SSYNC
I
Serial data frame synchronized signal (72 kHz) input from the CPU
57
SDOUT
O
Serial data output to the CPU
58
SCLK
I
Serial data transfer clock signal (9.216 MHz) input from the CPU
59
SDIN
I
Serial data input from the CPU
60
IRQ
O
Interrupt request signal output to the CPU
61
NC7
—
Not used
62, 63
GPIO4, GPIO5
I/O
Not used
64
DVDD2
—
Power supply terminal (+3.3V)
Содержание PEGA-CC5
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