Sony MDDISCAM DCM-M1, Руководство по обслуживанию

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DCM-M1
MAIN BOARD (1/7)
(SEE PAGE 4-29, 48, 53, 59)
CN8101 (1/3)
Y0 – Y7
C0 – C3
CAM_VD
CAM_HD
SPCKO
7
3
6
IO0
111
110
112
71
IN
STBY
Y VIDEO SIGNAL AMP
IC4004
Y VIDEO SIGNAL AMP
IC4003
OUT
4
1
IO1 72
IO3 84
EXVD
EXHD
VCLK
191
XABS
XARQ
190
ACDI 192
ACDO 194
RCK4 195
188 ACLK
XABS
XARQ
SYS_ACDI
SYS_ACDO
ACLK
C0/CIM0
AUDIO & VIDEO DATA CONTROL
IC8101
ID/CIN1
ADC8/CIN2
ADC9/CIN3
8
ı
15
16
ı
19
89
•
91
•
101
•
109
92
ı
98
•
100
ADC0/YIN0
ı
ADC7/YIN7
136 – 140
•
142 – 147
•
149 – 153
•
155 – 158
•
160 – 163
•
165 – 169
•
171 – 173
174 – 176
•
178 – 184
•
186
•
187
2 – 5 • 7 – 10 •
41 – 44
•
46 – 49
19 – 24 • 27 – 32
37 38 13 14
2 – 5 • 7 – 10 •
41 – 44
•
46 – 49
37 38 13 14
LCAS UCAS WE RAS LCAS UCAS WE RAS
19 – 24 • 27 – 32
SA0
–
SA11
SA0
–
SA11
SD16
–
SD31
SD0
–
SD15
DATA BUS
ADDRESS BUS
64M
EDO DRAM
IC8102
64M
EDO DRAM
IC8103
TO AUDIO
(SEE PAGE 3-18)
209
DSYNC
DCLK
203 MBCK
128 PLL OUT
212
222
211
123
MCLK
207
DDI
206
DDO 205
RCLK 189
SCLK 196
SCLK_SYS
SO 197
SI
198
MDTI 200
RAS 130
DWE 129
CAS0
135
CAS1 134
CAS2
132
CAS3 131
MLRCK
DSYNC
DCLK
DDI
DDO
SO
TO MD SERVO
(SEE PAGE 3-14)
TO MD SIGNAL
PROCESS
(SEE PAGE 3-12)
TO MD SIGNAL
PROCESS
(SEE PAGE 3-12)
SI
MDTI
MLRCK
202
512FS
1D
MBCK
2
X1CK 3
X1Q
D-FF
IC8104 (1/2)
6
2
BUFFER
Q4002
LPF
FL4002
IN
STBY
OUT
SAG
4
1
2
•
3
IN
STBY
C VIDEO SIGNAL AMP
IC4002
C VIDEO SIGNAL AMP
IC4001
COMPOSITE VIDEO
SIGNAL AMP
IC4005
OUT
4
1
2
BUFFER
Q4001
BPF
FL4001
BUFFER
Q4006
IN
STBY
OUT
4 2
1
VCC
8
Y IN
C IN
4
2
OUT1, 2
BUFFER
Q4005
IO2 83
BUFFER
Q4007
IC4006
IC4006
IC4009
IC4009
1 7
6 3
1 7
6 3
VHD 66
VVD 67
6
4
CN3002
(1/4)
3
10
12
6
4
CN3003
(1/4)
J4001
3
10
12
12
11
10
3
CN4313
(1/3)
4_JACK_DET
VIDEO OUT
S_C
S_JACK_DET
S_Y
4
SWITCH
Q4002, 4004
6
•
7
25
24
26
CN4511
(1/2)
23
27
PANEL_Y
LINE OUT R
LINE OUT L
PANEL_R-Y
PANEL_B-Y
LCD_XHD
LCD_XVD
EVF_Y
EVF_R-Y
EVF_B-Y
EVF_XHD
EVF_XVD
Y
C
S
G
G
S
S. VIDEO
J3003 (1/2)
AUDIO/VIDEO
JACK BOARD (1/4)
(SEE PAGE 4-119)
2Q
9
2D
D-FF
IC8104 (2/2)
12
RST
TRST
XCS
220 XINT
219
XWAIT
218 XWE0
217
XWE1
215 XWE2
214 XWE3
213
210
XRD
HANDI
FSY
HANDO
BITI
BITO
HANDO
HANDI
FSY_INT
MCLK_BUFF
SYS_BITI
SYS_BITO
S_JACK_DET
4_JACK_DET
S_OUT_OFF
C_OUT_OFF
32
33
34
36
X2CK 11
1Q 5 1D
D-FF
IC8020 (1/2)
2
X1CK
3
DRAMD0
ı
DRAMD31
2 – 4
•
224 – 227
•
229 – 233
•
235 – 240
•
242 – 248
•
250 – 256
5 – 8
•
10 – 15
•
17 – 23
•
25 – 29
•
31
DATA0
ı
DATA31
ADDR1
ı
ADDR23
DRAMA0
ı
DRAMA11
A0 ı
A11
DQ1
ı
DQ16
A0 ı
A11
DQ1
ı
DQ16
FSY_INT
TO SYSTEM CONTROL
(SEE PAGE 3-16)
SYSCHIP_INT
DEV_RESET
CPU_CS4_100
SYS_WAIT
DQMLL_WE0
RD
DQMUU_ICIOWR
DQMUL_ICIORD
DQMLU_WE1
54
•
52
ı
46
37
ı
41
•
43
ı
45
MEC0
ı
MEC7
MVP0
ı
MVP7
SYS_MVP0 – SYS_MVP7
MEC0 – MEC7
A0 – A23
D0 – D31
05
A
TO CAMERA SIGNAL
PROCESS
(SEE PAGE 3-4)
3
4
5
6
8
TO MPEG ENCODE
(SEE PAGE 3-9) 7
TO LCD
(SEE PAGE 3-19) E
TO EVF
(SEE PAGE 3-21) F
CHROMA Y
VIDEO SIGNAL
AUDIO
SIGNAL
Y/CHROMA MD1
REC
PB
MD2
MD SIGNAL
SIGNAL PATH
V
REC/PB
2.88 Vp-p
H
REC/PB
3.04 Vp-p
13.5 MHz
REC/PB
Approx.
3.4 Vp-p
3.1 Vp-p
V
REC/PB
H
REC/PB
3.6 Vp-p
H
REC/PB
2.32 Vp-p
H
REC/PB
360 mVp-p
H
REC/PB
1.48 Vp-p
27 MHz
REC/PB
3.52 Vp-p
H
REC/PB
700 mVp-p
H
REC/PB
1.12 Vp-p
3-7 3-8
3-4. A/V DATA CONTROL, VIDEO OUT BLOCK DIAGRAM