Sony IPELA SNC-RZ30N, Руководство по обслуживанию

Страница: 70 / 128

4-2
SNC-RZ30N (E)
4-1-5. System ROM
The system ROM (flash memory, IC009 and IC011) that has a capacity of 8 MB stores the data on the
operation program of HD6417615 (IC007), Web contents, or system environmental information. The
data is read and written by an SH data bus.
Since the system ROM is constituted by flash memory, it can upgrade software from a PC card through a
network.
4-1-6. System Memory
The system memory (SDRAM, IC008 and IC010) that has a capacity of 32 MB stores an HD6417615
(IC007) operation program or Web contents from flash memory when the power is turned on.
Other areas are used to secure an area of approximately 8 MB as internal memory.
The system memory also temporarily stores the JPEG compression data transferred from IC103 at high
speed using a DMA controller (IC007) or the saved image of an alarm buffer.
4-1-7. RTC Circuit
A dated watch function is realized using RTC (Real Time Clock) of IC001. The RTC is backed up by a
secondary battery (BT001). The watch data of RTC can be read and written by HD6417615.
4-1-8. Reset Circuit
A power-on reset signal is output to the HD6417615 (IC007), system ROM (flash memory, IC009 and
IC011), or PHY chip (IC301) using a reset circuit (IC002). The reset circuit also has a function for
outputting a reset signal using manual reset switch S002 or for outputting a reset signal by the detection
of a voltage decrease.
4-1-9. DIP Switch Block
DIP switch S001 is used to switch the operation mode of a system. When the power is on, HD6417615
(IC007) reads the state of the DIP switch so as to judge the operation mode. Usually, SW1 to SW4 are all
set to “0”.
In the test mode, SW1 to SW3 are all set to “1”, and SW4 is set to “0”.
4-1-10. Clock Buffer
Clock buffer IC006 buffers a clock of 30 MHz from SH CPU (IC007) and supplies a stable clock to the
system memory (SDRAM, IC008 and IC010) (SR1_CLK and SR2_CLK), PC card controller (IC201)
(PC_CLK), or MJPEG controller ASIC (IC103) (SYCLK).