Sony IPELA SNC-RZ30N, Руководство по обслуживанию

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4-1
SNC-RZ30N (E)
Section 4
Circuit Operation Description
4-1. SY-303 Board
4-1-1. Power Block
A power supply of 12 VDC is input from the DC jack of CN301 and sent to Q303 FET. In FET, the
power supply is cut when the polarity of AC adaptor power is incorrect. The 12 VDC power passed
through FET is sent from CN401 (pin 8) to the MDR-19 board and from CN404 (pin 21) to the camera
module. Moreover, a power (of 3.3 VDC and 5 VDC) is supplied to each IC on the SY-303 board
through CN405 (pin 12) on the MDR-19 board.
4-1-2. Analog Video Output Circuit
An analog video signal (VBS_OUT) is output through CN404 from the BNC connector (CN303).
4-1-3. Digital Image Data Processing Circuit
The digital image data processing circuit outputs the interlaced YUV411 digital image data (CAMY[7:0]
and CAMC[3:0]) and control signal (CCLK) and inputs them from the camera module to MJPEG
controller ASIC (IC103) through CN402. In IC103, an image format is converted into YCbCr422, and
frame data is written in SDRAM (IC102). The conversion of interlacing to non-interlacing and the data
conversion such as square latticing and resizing are performed to make a raster block conversion using a
buffer (SRAM, IC101). The resultant data is sent to JPEG IC (IC104). Data is JPEG-compressed in
JPEG IC (IC104.)
IC103 incorporates a DMA interface with IC007 HD6417615 (CPU). IC103 transfers the JPEG
compression data to SDRAM (IC008 and IC010) by DMA (XSH_DREQ and XSH_DACK) and stores it
at high speed. SH bus address decoding, external interrupt control or external wait control is provided.
The control signals from each IC are input to IC103 and output to SH-CPU (IC007) after it is controlled.
IC103 also has an internal dynamic detector.
4-1-4. Outline of SH-CPU Operation
HD6417615 (CPU, IC00) jmainly controls the access to MJPEG controller ASIC (IC103), system
memory (SDRAM, IC008 and IC010), system ROM (flash memory, IC009 and IC011), a PC card
controller (IC201), and a PHY chip (IC301). It also transfers data (JPEG image data) via a network or
records data in a PC card. Moreover, HD6417615 performs the Visca communication control with a
motor control block (H8 microcomputer on the MDR-19 board), the external interface (RS-232, RS-485,
sensor input, and alarm output) control, the LED control, the clock generation (output of a 30 MHz clock
to IC006), the interrupt control, the RTC (IC001) control, the software reset (XSRST) control.