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SLG46140
9.8 ADC Outputs
The ADC’s output can be shifted out through the SPI logic cell. Both SER DATA and PAR DATA produce an 8-bit data string over
16 clock cycles. See
9.8.1 ADC Serial Output
The 8-bit serial data can be output from the SLG46140 device on PIN 12. The individual 8 serial data bits can be read into an
external device within the larger system design.
To initialize the
SER DATA
the ADC needs a Power Down signal, which can be configured through the connection matrix. After
6 ADC_CLK cycles the ADC will start to output the 8-Bit Serial Data. This PD signal needs to be held for at least 16 ADC_CLK
cycles. The ADC_CLK is determined by either the RC Osc, Ring Osc, Matrix_Out67, or SPI CLK.
9.8.2 ADC Parallel Output
The 16-bit parallel data can be output from the ADC logic cell to either the DCMP/PWM or FSM logic cells within the SLG46140
device.
To initialize the
PAR DATA
the ADC needs a Power Down signal, which can be configured through the connection matrix. After
ten ADC_CLK cycles the ADC will start to output the 16-Bit Parallel Data. This PD signal needs to be held for at least 32 ADC_CLK
cycles. The ADC_CLK is determined by either the RC Osc, Ring Osc, Matrix_Out67, or SPI CLK.
Figure 34. ADC Clock Source
0
1
/16
ADC CLK SRC reg <580:579>
00
01
10
11
Ring Osc
Matrix Out <67>
RC Osc
SPI CLK
reg <578>
CLK
Содержание GreenPAK SLG46140
Страница 102: ...000 0046140 111 Page 101 of 169 SLG46140 14 1 Initial Polarity Operations Figure 54 DFF Polarity Operations ...
Страница 103: ...000 0046140 111 Page 102 of 169 SLG46140 Figure 55 DFF Polarity Operations with nReset ...
Страница 104: ...000 0046140 111 Page 103 of 169 SLG46140 Figure 56 DFF Polarity Operations with nSet ...
