Silego GreenPAK SLG46140, Руководство пользователя

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SLG46140
5.5 Typical Delay Estimated for Each Macrocell
Table 1. Typical Delay Estimated for Each Macrocell
Symbol Parameter Note
VDD=1.8V VDD=3.3V VDD=5.0V Unit
Rising
Falling
Rising Falling Rising
Falling
tpd Delay LUT 2-bit 17.43 15.33 6.31 6.09 4.20 4.31 ns
tpd Delay LUT 2-bit (Shared with DFF/Latch) 21.53 20.67 8.13 8.33 5.45 6.01 ns
tpd Delay LUT 3-bit 18.49 15.69 6.74 6.31 4.49 4.52 ns
tpd Delay LUT 3-bit (Shared with DFF/Latch) 23.04 21.51 8.74 8.75 5.86 6.37 ns
tpd Delay LUT 3-bit (Shared with Pipe Delay) 25.65 24.01 9.37 9.47 6.67 7.32 ns
tpd Delay LUT 3-bit (Shared with CNT/DLY) 23.17 20.67 8.62 8.32 5.73 6.05 ns
tpd Delay LUT 4-bit (Shared with PGEN) 21.13 22.27 9.07 8.97 6.04 6.46 ns
tpd Delay LUT 4-bit (Shared with CNT/DLY) 25.42 22.29 9.54 9.02 6.41 6.59 ns
tpd Delay DFF (Shared with 2-bit LUT) 27.25 28.68 10.67 10.78 7.30 7.51 ns
tpd Delay DFF (Shared with 3-bit LUT) 27.87 28.96 10.87 10.93 7.44 7.61 ns
tpd Delay
DFF (Shared with 3-bit LUT) nRe-
set
-- 29.84 -- 12.41 -- 8.95 ns
tpd Delay DFF (Shared with 3-bit LUT) nSet -- 36.73 -- 14.00 -- 9.42 ns
tpd Delay DFF 23.01 23.77 8.91 8.73 5.95 6.15 ns
tpd Delay DFF nReset -- 23.64 -- 9.71 -- 7.11 ns
tpd Delay DFF nSet -- 31.5 -- 11.4 -- 7.68 ns
tpd Delay
CNT/DLY opposite to selected
edge delay
46.61 36.87 18.56 15.62 12.53 11.23 ns
tpd Delay
CNT/DLY (Shared) opposite to se-
lected edge delay
47.30 37.16 18.78 15.78 12.68 11.77 ns
tpd Delay CNT/DLY Both edge detect 49.5 52.9 20.07 20.84 13.81 14.32 ns
tpd Delay CNT/DLY Rising edge detect 52.39 -- 21.32 -- 14.67 -- ns
tpd Delay CNT/DLY Falling edge detect -- 55.94 -- 22.15 -- 15.27 ns
tw Width CNT/DLY Both edge detect 25.17 24.93 11.98 12.01 8.76 8.83 ns
tw Width CNT/DLY Rising edge detect 25.76 -- 12.14 -- 8.86 -- ns
tw Width CNT/DLY Falling edge detect -- 24.51 -- 11.79 -- 8.57 ns
tpd Delay Latch (Shared with 2-bit LUT) 26.25 25.43 10.2 10.43 6.99 7.58 ns
tpd Delay Latch (Shared with 3-bit LUT) 26.93 25.72 10.42 10.6 7.11 7.72 ns
tpd Delay
Latch (Shared with 3-bit LUT) nRe-
set
-- 31.8 -- 13.17 -- 9.61 ns
tpd Delay Latch (Shared with 3-bit LUT) nSet -- 34.23 -- 12.97 -- 8.76 ns
tpd Delay Latch 21.28 19.87 8.17 8.13 5.51 5.92 ns
tpd Delay Latch nReset -- 25.45 -- 10.52 -- 7.74 ns
tpd Delay Latch nSet -- 28.36 -- 10.37 -- 6.76 ns
tpd Delay Pipe Delay (Shared) 33.44 34.93 13.39 13.21 9.40 9.17 ns
tpd Delay Pipe Delay (Shared) nReset -- 35.42 -- 15.07 -- 11.24 ns
tpd Delay PGEN (Shared) 22.44 23.52 8.69 9.00 5.77 6.01 ns
tpd Delay PGEN (Shared) nReset to 0 -- 21.73 -- 8.88 -- 6.60 ns
tpd Delay PGEN (Shared) nReset to 1 22.81 -- 9.75 -- 6.99 -- ns
tpd Delay PDLY 1Cells Both edge detect 30.71 35.23 12.00 13.45 8.42 9.26 ns
tpd Delay
PDLY 1Cells delayed output Both
edge detect
191.41 195.73 75.44 76.67 48.41 49.32 ns