©2018
Rev 2.0
29
Hardware Registers
Bits Type Name
Width Description
[0]
W
LockEnable
1
0 = Uses internal 10 MHz TCXO
1 = Enables frequency locking to external 10 MHz
reference source
[1]
W
RefOutEnable
1
Reference out port enabled
[2]
W
Clk10Enable
1
0 = 10 MHz output
1 = 100 MHz output
[3]
W
PXI10Enable
1
Only on SC5309A to enable export of the 10 MHz
backplane clock
[7:2]
W
Unused
4
Set to zeros
[7:0]
R
Read back byte
8
Read 1 byte back is required for PXIe and RS232
Register 0x19 REFERENCE_DAC
This register makes adjustments to the 10 MHz TCXO accuracy via DAC to its tuning port.
Bytes written 4
Bytes read 1
Bits Type Name
Width Description
[15:0]
W
Tuning DAC word
16
DAC WORD
[23:16]
W
Unused
8
Set to zeros
[7:0]
R
Read back byte
8
Read 1 byte back is required for PXIe and RS232
Register 0x1A FREQ_PLAN_PARAM
This register sets up the frequency plan parameters and stores them as the default values.
Bytes written 8
Bytes read 1
Bits Type Name
Width Description
[47:0]
W
Data
48
Data for the parameter
