PC-UM10M
SL-5500 HARDWARE DESCRIPTION
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3. ABOUT THE SYSTEM OF SL-5500
3-1. SYSTEM OUTLINE
3-2. AUDIO CONTROL
At this time, the clock signal inputted into GPIO19 is used as the syn-
chronous clock signal.
DAC is controlled using GPIO of GA.
/ML :PCM_SLOAD (GPIO12)
MC :PCM_SCK (GPIO11)
MD :PCM_SDATA (GPIO10)
3-3. SERIAL CONTROL
The 16-pin connector has two modes: serial and JTAG. The two modes can be switched over using the pin 13.
Pin assignment of 16 pins
• When the pin 13 is at LOW, the connector operates in the serial
mode.
• Wakeup from 16-pin serial
Wakeup can be performed using the signal from the pin 10 of the 16-
pin connector.
This causes an event at CPU-GP24 when SW at the cradle is
pressed. (Active LOW)
Item
SL-5500
CPU
SA1110 Rev.B4
ROMP capacity
(x32 bus fixed)
nCS0
3
16MB
nCS1
3
Not Use
nCS2
3
Not Use
nCS3
3
Not Use
PC slot A
3
CF
NCS4
3
GA/CF_GA
NCS5
3
Not Use
RAM capacity
(SDRAM)
nMCS0
3
64MB
nMCS1
3
Not Use
nMCS
3
Not Use
Optical communication
IrDA1.2 (115kbps)
Sharp:GP2W0110YP
USB (slave only)
USB1.1 (16-pin connector)
Touch panel
Resistance sheet type
LCD
HR-TFT
320 x 240 dots
SD card
Yes
CF card
Type
ΙΙ
F/L brightness control
function
Front CCFL
Duty light control/VR (current) light control
AUDIO
Sounder & earphone jack
DAC:PCM1741
AMP:NJM2172
Analog
TC35143AF
16-pin connector
Charger power supply
USB (Function)
Serial & JTAG (switchable)
CPU
CLK64fs
SCLK
SFRM
SDOUT
GA
CLK64fs
MCLK
SCLK
SCK
SFRM
LRCLK
DAC
XTI
BCKIN L
LRCIN R
DIN
AMP
JACK
MUTEcontrol
DAC M62332FP
VR
ML
MC
MD
GPIO12
GPIO11
GPIO10
/ML
MC
MD
GA
DAC
ML
MC
MD
LSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
13pin
L
PWR
PWR
TXD
RXD
RTS
CTS
DSR
GND
USB
D+
WU
VCC
3.3V
USB
D–
TRST
DTR
PWR
PWR