PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 17 –
(4) PIN FUNCTION
(4)-1. PIN DESCRIPTION BY FUNCTION (128-PIN SPECIFICATION)
Function
Pin name
Pin No.
Q'ty
I/O
Buffer
Description
Connected to
SA1110
interface
( V a r i a b l e
Latency I/O)
BATTFAULT
1
IN
IBC
Battery voltage detection input
Detection circuit
PWREN
1
IN
IBC
CPU status input (L: HALT, H: Operate)
RESET_B
1
IN
IBH
Reset input
CPU (SA1110)
RTC32K
1
IN
IBO
RTC 32 kHz clock signal input
CPU (SA1110)
CS_B
1
IN
IBO
Chip selection signal for GA
CPU (SA1110)
WE_B
1
IN
IBO
Write enable signal for GA
CPU (SA1110)
OE_B
1
IN
IBO
Output enable signal for GA
CPU (SA1110)
ADR[25:23]
3
IN
IBO
Address bus
CPU (SA1110)
ADR[7:2]
6
IN
IBO
Address bus
CPU (SA1110)
DATA[15:0]
16
IN/OUT
BA2T
Data bus
CPU (SA1110)
Subtotal
32
Interrupt control
INT_B
1
OUT
OB1T
INT (including interrupt key) output signal
CPU
(SA1110 interrupt)
BOOT drive
switching
circuit and
decode
CS[1:0]_B
2
IN
IBO
CS signal for FROM/MROM signal
CPU (SA1110)
MCS0[3:0]_B
4
OUT
OB1T
MCS signal 0 for FROM/MROM decode signal
FROM/MROM
MCS1[3:0]_B
4
OUT
OB1T
MCS signal 1 for FROM/MROM decode signal
FROM/MROM
FROM_B
1
IN
IBOP2
FROM_Board detection pin
FROM/MROM
Subtotal
11
Key port circuit
KSTRB[7:0]
8
OUT
TB1HT
Key strobe signal
KEY_BOARD
KI_B[15:0]
16
IN
IBH
Key input signal
(external pull-up resistance is required)
KEY_BOARD
Subtotal
24
Serial output
circuit for
general-purpose
8-bit 2ch DAC
control
SCL
1
OUT
OD1T
Serial clock signal
DAC
SDA
1
IN/OUT
BG1
Serial data
DAC
Subtotal
2
TFT_C reset
TFTRESET
1
OUT
OB1T
TFT_C reset signal
TFT PS control
CPS
1
OUT
OB1T
TFT power save CPS output signal
TFT panel
AD_START
output circuit for
tablet control
ADSTART
1
OUT
IBO
Tablet incorporation START signal
Toshiba TC35143AF
HS
1
IN
IBO
LCD horizontal synchronous signal
CPU
(SA1110-I, CDC)
DCLK
1
IN
IBO
LCD data transfer clock signal
CPU
(SA1110-I, CDC)
Subtotal
3
PWM output
port
TIMEOUT
1
OUT
OB2T
Battery charger protection timer
Charger circuit
LEDPWM0
1
OUT
OB2T
For charger indicator
Charger circuit
LEDPWM1
1
OUT
OB2T
For communication error blinking
Charger circuit
FLPWM
1
OUT
OB1T
F/L Duty light control signal (0-100%) output
F/L inverter circuit
Subtotal
4
Audio
MCLK/SCK32
output port
XIN22M
1
IN
LIN
44.1 KHz system base clock input
(22.5792 MHz)
Oscillation circuit 1
(OSC4C)
XOUT22M
1
OUT
LOT
44.1 KHz system base clock output
(22.5792 MHz)
Oscillation circuit 1
(OSC4C)
XIN24M
1
IN
LIN
48 KHz system base clock input (MHz)
Oscillation circuit 2
(OSC4C)
XOUT24M
1
OUT
LOT
48 KHz system base clock output
(22.5792 MHz)
Oscillation circuit 2
(OSC4C)
CLK64FS
1
OUT
OB2T
Audio 64 fs output (SCLK x2)
CPU (GPI0)
MCLK
1
OUT
OB2T
Audio MCLK clock output
Audio DAC
Subtotal
6
