PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 10 –
(4) PIN DESCRIPTION
(5) PIN FUNCTION
GPIO0
N.C.
DVSS1
-RST
SSYNC
SDOUT
SCLK
SDIN
IRQ
N.N.
GPIO4
GPIO5
DVDD2
GPIO1
GPIO2
GPIO3
AVDD4
TELOP
AVDD3
N.C.
VREF
MICBIAS
AVSS2
VBIN2N
VBIN2P
VBIN1N
VBIN1P
AVDD2
N.C.
N.C.
AVSS3
TELON
DVDD1
TSMY
TSMX
TSPY
AVSS5
AIN0
CVSS2
AVSS4
TELIN
TELIP
EXRINT
AVDD5
TSPX
GPIO6
AD
SYNC
TEST2
TEST1
DVSS2
N.C.
CVSS1
AVDD1
VBO1P
VBO1N
VBO2P
VBO2N
AVSS1
GPIO7
GPIO8
GPIO9
AIN1
AIN2
AIN3
49
33
48
32
64
17
1
16
TOP VIEW
Symbol
Pin No.
A/D/P
I/O
DEF
Group
Deption
SCLK
58
D
I
–
HOST
Serial data transfer clock. Serial data is transferred synchronizing with this clock.
SCLK is used as the master clock for TC35143AF. The specification of SCLK is 9.216 MHz,
with duty ratio 50%. Connect to the clock output of SIB master chip.
SSYNC
56
D
I
HOST
This signal provides synchronization for serial data frames. 72kHz clock. 1 frame consists
of 128 bits of serial data. Connect to the synchronizing signal output of SIB master chip.
SDIN
59
D
I
HOST
Serial input data terminal. Serial data input through the SDIN terminal is latched inside at
the falling edge of SCLK. Connect to the data output of SIB master chip.
SDOUT
57
D
O
HZ
HOST
Serial output data terminal. Serial data output through SDOUT terminal is output, synchro-
nizing with the rising edge of SCLK. Connect to the data input of SIB masterchip.
IRQ
60
D
O
L
HOST
Interrupt output terminal. Interrupt factors output from the control resistor to this terminal
are set. The signal level at the time of interrupt is active high.
RST
55
D
I
–
HOST
System reset. This signal is active low.
TSPX
45
A
I/O
HZ(IN)
TSC
Interface terminal for touch screen X plate. Open when not in use.
TSMX
43
A
I/O
HZ(IN)
TSC
Interface terminal for touch screen X place. Open when not in use.
TSPY
42
A
I/O
HZ(IN)
TSC
Interface terminal for touch screen Y plate. Open when not in use.
TSMY
44
A
I/O
HZ(IN)
TSC
Interface terminal for touch screen Y plate. Open when not in use.
AIN0
40
A
I
–
ADC
ADC input
AIN1
39
A
I
–
ADC
ADC input
AIN2
38
A
I
–
ADC
ADC input
AIN3
37
A
I
–
ADC
ADC input
ADSYNC
5
D
I
–
ADC
Synchronizing clock input terminal when putting 10-bit ADC in the external clock synchro-
nizing mode. ADC starts conversion synchronizing with the edge of ADSYNC.Pull down
when not in use.
EXRINT
47
A
I
–
TSC
Terminal to which external resistance is connected, for adjusting detection sensitivity in
touch detection mode. Connect a resistance of more than 16k
Ω
between AVDD5.
TELOP
28
A
O
HZ
TEL
Positive polarity output terminal for telephone line CODEC
TELON
29
A
O
HZ
TEL
Negative polarity output terminal for telephone line CODEC
TELIP
33
A
I
–
TEL
Positive polarity input terminal for telephone line CODEC. Open when not in use.
TELIN
34
A
I
–
TEL
Negative polarity input terminal for telephone line CODEC. Open when not in use.
VBO1P
12
A
O
HZ
VB
Positive polarity output terminal 1 for sound CODEC. It is used for the handset speaker.
VBO1N
13
A
O
HZ
VB
Negative polarity output terminal 1 for sound CODEC. It is used for the handset speaker.