PC-UM10M
SL-5500 HARDWARE DESCRIPTION
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(2)-2. SPI I/F
(2)-2-1. Outline
This module interfaces SD card and MMC in the SPI mode and has the
following features:
• Capable of interfacing multiple SD cards and MMCs. However, since
there is a single spics_b, control is required using GP10 and others.
• spidi needs a pull-up resistance outside.
• Clock synchronous type serial port and data length can be selected
between 8 and 16 bits.
The data length set forth in this specification is called unit.
• Double buffers for transmission and reception (no FIFO) make it pos-
sible to perform transmission and reception continuously.
• In transmission and reception, it is possible to select whether data
alignment (transmission and reception synchronized in the unit of
“unit”) is carried out or not can be selected.
• Clock frequency can be selected from among 15 bands (24.576MHz -
2.304MHz and 384 kHz - 288 KHz).
• There are 4 interrupts including reception data read enable, transmis-
sion data write enable, transmission end, and reception end. They
can be separately allowed or prohibited.
• When this module is not in use, clock can be stopped to reduce
power consumption.
• MSB/LSB first can be selected.
• Transmission and reception bit can be freely reversed.
• Test can be performed by looping back the status of spido to spidi,
without suing any jig.
• The timing between transmission and reception data and clock can
be set. The status of spido can be set after data is transmitted or
received or while data is only received.
• This module is not affected by pwren, but when battfault is at L, it is
reset.
(2)-2-2. Block diagram
Here is a block diagram of this module.
(2)-3. FRONT LIGHT CONTROL
(2)-3-1. Outline
• This module outputs the pulse modulation output signal for controlling
the front light DUTY. It has the following features:
• Front light DUTY control pulse modulation output (Cycle and DUTY
can be changed)
• Fixed output at PWREN and internal Enbit
• Inverted output at INVbit is possible
• When BATTFAULT pin input level is Low, the register of this module is
initialized.
(2)-3-2. Block diagram
(2)-4. LED CONTROLLER
(2)-4-1. Outline
This module outputs the pulse modulation output signal for LED light
emission to the LEDPWM0, 1 pins. It has the following features:
• Outputs the pulse modulation output signal for LED light emission to
the LEDPWM0, 1 pins. Cycle and DUTY can be separately changed.
• When the BATTFAULT pin input level is at Low, the register of this
module is initialized.
(2)-4-2. Block diagram
(2)-5. TOSHIBA ANALOG FRONT END LSI OSCILLATION
CIRCUIT
(2)-5-1. Outline
This module outputs 9.216MHz clock signal to Toshiba analog end LSI
(TC35143AF). It has the following features:
• Outputs 9.216MHz clock signal from LCK9M pin.
• The registers of this module are initialized when BATTFAULT pin input
level is at LOW.
• This module is not affected by pwren pin input.
• Capable of monitoring the same signal as that from CLK9M pin using
the status register (04h) bit1 (clk9m).
(2)-5-2. Block diagram (Here is a circuit image.)
spimod
spictl
spiint
clkgen
GPIO
spitxd
spirxd
spitsd
spirsd
DI
DO
WP CD
CS
SCLK
spics_b (2)
spiif
interrupt
24.576MHz
22.5792MHz
18.432MHz
LoCoMo
spiclk
spics_b
spidi
spido
Oscillation
control
moduel
CPU bus
PWB
Transmission and
reception control
Register
SD card
/ MMC
#2
SD cards
/ MMC
#1
Power
supply
INV
EN
HSYEN
BPDF
8-0
BPWF
7-0
HSYS signal
(touch panel
control)
rtc32k
input pin
CPU bus
Internal flpwn
signal
Register setting
Initialize
pwren input pin
flpwm output pin
battfault input pin
Inversion
function
LEDPWM1
LEDPWM0
CLK32K
Internal ledpwm signal
Register setting
CPU bus
Initialize
ledpwm0 output pin
ledpwm1 output pin
battfault input pin
CLK9MEN
XON
Initialize
Xout 18m
output pin
Xin 18m
input pin
CPU bus
1/2
dividing
circuit
Register settings
to Xout 18 (18.432 MHz)
SPI/CLK32K block
Internal status register
bit 1(CLK9M)
CLK9M output pin
battfault input pin
SPI block
XON signal
CLK32K block
XON signal