or up to 8 bits per pixel are required, the designer
must provide external shift registers. Video RAM
components may also be considered.
In either case, the user must design :
- A memory block. This is the hardware memory
building block. It includes the video shift registers
if on-chip VSR cannot be used. It implies a RAM
component choice.
- An Address Mapper, which maps the logical ad-
dress into hardware address : block selection,
Row Address (RAD), Column Address (CAD).
- A memory cycle controller. This controller moni-
tors the CYF and CYS output pins from TS68483
and block address from the Mapper. It provides :
- The CLK signal to the TS68483 and a shift clock
SCLK when external video shift registers are
used
- RAS, CAS, OE, R/ W signals to the memory
blocks
- RAD and CAD Enable signals to the Mapper.
V.3.1 - FRAME BUFFER (see Table 6)
A byte wide organization of each bit plane is re-
quired. Obviously a bit plane must contain the
Display Viewport size. A straight organization im-
plements only one bit plane per block.
It may be cost effective to implement several bit
planes per block. Two basic schemes may be
used :
- One block, one Z : several bit planes, belonging
to different banks, but addressed by the same Z,
share a given block. There is little time constraint
if any.
- One block, two Z : two bit planes, belonging to the
same bank share a given block. In this case, this
block must be accessed twice during a memory
cycle. This can be solved by two successive page
mode accesses.
Table 5 : Memory Cycle Types
Output Pins
Function
Modx Flags
Multiplexed ADM
Cycle Type
CYF1
CYF0
1
0
TA
TO
T1
1
0
Command Read
Y,X
Z0,Z2
Z1,Z3
Read
1
1
Command Write
Y,X
Z0,Z2
Z1,Z3
Write
0
1
Display
0
0
0
1
Y,X
Y,X
Z0,Z2
Z1,Z3
Read
Dummy Read + 1
0
0
Refresh
1
1
0
1
Y,X
Y,Hi-Z
Dummy Read + 2
Float X
Refresh : dummy read cycle is performed.
68483-08.TBL
Table 6 : Frame Buffer Organization
Typical Block Size
16 k x 8
32 k x 8
64 k x 8
256 k x 8
One Block-one Bit Planes
512 x 256
512 x 512
1024 x 512
2048 x 1024
One Block-two Bit Planes
256 x 256
512 x 256
512 x 512
COMPONENTS : 64K BITS : 16K x 4 or 64K x 1
256K BITS : 32K x 8, 64K x 4, 256K x 1
VIDEO RAM : 64K x 1, 64K x 4
68483-09.TBL
Table 7 : The Multiplexing Scheme
HIGHER BYTES
ADMS Multiplexed Pins
15
14
13
12
11
10
9
8
TA : Address Period
10
X
3
T0 : Even Z Byte Period
7
Z = 2
0
T1 : Odd Z Byte Period
7
Z = 3
0
LOWER BYTES
ADMS Multiplexed Pins
7
6
5
4
3
2
1
0
TA : Address Period
10
Y
3
T0 : Even Z Byte Period
7
Z = 0
0
T1 : Odd Z Byte Period
7
Z = 1
0
68483-10.TBL
TS68483A
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