SGS TS68483A, Руководство пользователя

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IV.2.4. MEMORY TIME SHARING (see Figure 16)
7T TL
BLKX
HORIZONTAL
Horizontal Minimum
Number of Cycles
BKX
FFX
DWX
H 4
3
3
19
3T BKX
FPX
FRONT
PORCH
DWX DISPLAY
BACK
PORCH
1T 2T
Vertical Minimum
Number of Lines
FPY
DWY
BPY
BKY 1
1
3
1
MARGIN
DISPLAY
BLANKING
BLANKING
FRONT
PORCH
FPY
DISPLAY
DWY
BACK
PORCH
= BPY - 25
BKY
25 Lines
2H
BLKY
68483-18.EPS
Figure 16 : Video Programming
The Video Timing Generator allocates memory
cycles to either the display process, RAM refresh
or command execution. In this respect, the scan
lines per field are split between : the DWY display-
able lines.
When VRE = 0, Video RAMs are not used.
The DWY x DWX cycles in the display interval are
allocated to the display process when it is enabled
(DPD = 0). When the display process is disabled,
these cycles are allocated as for non displayable
lines.
When VRE = 1, one cycle per display line is allo-
cated to the display process. Other cycles are
allocated as for non displayable lines. The last
period of the BLKX signal may be used to load the
internal video RAM shift register.
- the non displayable lines. In one out of nine non
displayable lines, DWX cycles are allocated to the
refresh process when it is enabled (RFD = 0).
- In Float cycle, an external X address must be
provided. The Y address is still provided on
ADM(0:7) and Y(0:2), while ADM(8:15) are in high
impedance state.
IV.2.5. COMMAND ACCESS RATIO
This allocation scheme leaves about 50% of the
memory bandwidth for command access when
programming a standard TV scan. This ratio drops
to the 30% range when a better monitor is in use
(32
µ
s out of 43
µ
s displayable per line, 360 lines out
of 390 for a 60Hz field rate). The higher resolution
means more memory accesses in order to edit a
given percentage of the screen area. In this case
Video RAMs are very helpful to keep 90% of the
memory bandwidth available for command access.
IV.3 - Display Process
The Video Timing Generator allocates memory
cycles to the Display Processor in order to read the
Display Viewport from memory. The Display View-
port upper left corner address is programmable
through DIB, YOR and XOR. The display viewport
dimensions are related to the display interval of
DWY lines by DWX cycles per field.
TS68483A
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