ADM (0 : 15), B (0 : 1), CYF (0 : 1), Y (0 : 2), CYS
V
CC
= 5.0V
±
5 %, T
A
= T
L
to T
H
, CLK Duty Cycle = 50 %, Period T
Reference Levels : V
IL
= 0.8V and V
IH
= 2V, V
OL
= 0.4V and V
OH
= 2.4V
Indent Number
Parameter
Min.
Max.
Unit
1
TCLK Clock Period
55
166
ns
2
Memory Cycle Time (T = 8 X T
CLK
)
ns
3
Output Delay Time from CLK
35
ns
4
Output Data HI-Z Time from CLK
35
ns
5
Output Hold Time from CLK
10
ns
6
Input Data Hold Time from CLK (read cycle)
6
ns
7
Input Data Set up Time from CLK (read cycle)
10
ns
8
Input Data HI-Z Time from CLK
T
CLK
ns
Note : All timing is referenced to the rising edge of CLK (see timing diagram 3).
68483-13.TBL
VI.2 - Memory Interface
1
3
2
4
4
3
3
3
5
5
4
5
7
7
6
8
6
8
CLK
CYS
B [0:1]
CYF [0:1]
Y [0:2]
ADM [0:15]
WRITE CYCLE
ADM [0:15]
READ CYCLE
ADM [0:15]
DUMMY READ CYCLE
DISPLAY
FLOATING
CYCLE
ADM [0:7]
ADM [8:15]
A (X, Y)
A (X, Y)
A (X, Y)
A (Y)
D (EVEN Z)
D (EVEN Z)
D (ODD Z)
D (ODD Z)
68483-27.EPS
Figure 25 : Memory Interface
TS68483A
25/30
