15
14 13 12 11 10
9
8
STATUS REGISTER R12
MASK NSEM
NSEM
MASK SEM
SEM
MASK VS
VS
MASK FREE
FREE
READ ONLY
15 14 13 12 11 10
9
8
R12
IRQ
68483-14.EPS
Figure 12 : Status Register
III - MICROPROCESSOR INTERFACE
III.1 - Introduction
The TS68483 is directly compatible with any popu-
lar 8 or 16-bit host microprocessor ; either Motorola
type (6809, 68008, 68000) or Intel type (8088,
8086).
The host microprocessor has direct access to any
of the twenty four 16-bit on-chip registers through
the microprocessor interface pins :
- D(0:15) : 16 bidirectional data pins.
- A(0:7) : 8 address inputs
- AE, DS, R/ W, CS : 4 control inputs.
The twenty four registers are mapped in the host
addressing space as 256 byte addresses (see
Figure 13)
- A(1:5) select one out of 24 registers.
- A0 selects the low order byte (A0 = 1) or the high
order byte (A0 = 0) of the selected register.
- A(6:7) provide the command execution condition.
The host microprocessor bus may be either 8 or
16-bits wide and may be address/data multiplexed
or not.
The two flags MB and BW in the CONFIGURATION
register R10 allow the data bus size and multi-
plexed/non-mutiplexed organization to be speci-
fied (see Table 2).
Table 2 : MPU Selection
Type of MPU Bus
Conf. Reg.
TS68483 Pins
BW
MB
AE
DS
R/W
AO
A (1 : 7)
D (8 : 15)
Non Mux
16-bit (68000)
0
0
1
UDS or LDS
R/W
O
A (1 : 7)
D (8 : 15)
8-bit (68008)
1
0
1
DS
R/W
AO
A (1 : 7)
D (0 : 7)
Mux
16-bit (8086)
0
1
ALE
RD
WR
O
AD (1 : 7)
AD (8 : 15)
8-bit (8088)
1
1
ALE
RD
WR
ADO
AD (1 : 7)
AD (0 : 7)
68483-05.TBL
15
14
13 12
11 10
9
8
7
6
5
4
3
2
1
0
A0 = 0
A0 = 1
Byte Addressing
A7 A6 A5 A4 A3 A2 A1 A0
High/Low Byte Address
16-bit Register ADDRESS
Execution Condition
68483-15.EPS
Figure 13 : On-chip Address and Byte Packing
TS68483A
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