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SGS TS68483A, Руководство пользователя

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SGS TS68483A Скачать руководство пользователя страница 7

II.2 - Pointers and Geometric Arguments (see
Figure 4)
Pointers are used to specify main geometric argu-
ments and display memory addresses.

II.2.1 - DISPLAY MEMORY ADDRESS
A bit in the display memory is addressed by :
- a bank number

B = 0 to 3

- a plane number

Z = 0 to 3

- an X address

X = 0 to 2047

- a Y addres

Y = 0 to 2047

II.2.2 - DESTINATION POINTER :
Registers R14 to R17

This pointer gives the coordinate (Xd, Yd) and
dimension (DXd, DYd) of either a line or a window
in the drawing coordinate system. These drawing
coordinates are easily mapped into a PEL DIS-
PLAY MEMORY address.

(X, Y) coordinates are clipped to 11 bits in order to
get the Xd, Yd destination pel addresses.

A bank number Bd must be explicitly provided to
address a destination frame buffer. When long pels
are used, Bd must be even.

When masked pels are used, the destination mask
plane number Zd (implicitly in bank 3) must also be
provided.

II.2.3 - SOURCE POINTER : Registers R20 to R23.

A source cell such as a character, a pen or an
object, is addressed by the source pointer in the
display memory.

A source pointer specifies :
- a bank number Bs = 0 to 3

- a Ys address Ys = 0 to 2047
- an Xs address ; this address is a byte address so

that the 3 LSBs are not specified Xs = 0 to 255

- a cell dimension DXs, DYs
- a bit plane address Zs.

When a character is addressed, Zs gives the plane
number into the bank Bs. When an object is ad-
dressed Zs gives the source mask plane number
in the bank B3.

II.2.4 - NOTES :
1. The TRAPEZIUM command makes a special

use of R21. In this case, R21 holds an X1
drawing coordinate which has the same format
as Xd.

2. The ARC and POLYARC commands require

two extra geometric parameters (RAD and
STOP). They are specified in the drawing
coordinates system and stored in registers R18,
R19.

3. Any drawing command may be parametered to

use short incremental dimensions, DXY in
register R13 instead of the standard DXd, DYd
in the ”R16, R17” register pair (see Figure 5).

4. The access commands use the destination

pointer location as a data buffer. The memory
addresses and dimension of the access
viewport are then specified in the source
pointer, independently of the data transfer.

5. DXd, DYd and DYs may specify a negative

value. In this case, they must be coded by a sign
(0 = positive, 1 = negative) and an 11-bit
absolute value.

Table 1 : Command Set Structure

Command

Drawing Mode

Type

Group

Line
Arc

Up to the Pen

Linear

Drawing

Rectangle
Trapezium
Polygon
Polyarc

Monochrome

Area

Print Char
Print Object

Bichrome
Polychrome

Cell

Load Viewport
Save Viewport
Modify Viewport

Access

Management

Move Cursor Abort

Control

68483-04.TBL

TS68483A

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Содержание TS68483A

Страница 1: ...OR PEN CONCEPT AND PROGRAMMABLE LINE STYLE FLEXIBLE AREA FILL COMMAND WITH TILING PATTERN VERY FAST BLOCK MOVE OPERATION CHARACTER DRAWING COMMAND ANY SIZE AND FONTS AVAILABLE LARGE FRAME BUFFER ADDR...

Страница 2: ...onnected to the WR signal CS I Chip Select This input selects the TS68483 registers for the current bus cycle A low level corresponds to an asserted chip select In multiplexed mode this input is strob...

Страница 3: ...Voltage 0 3 7 0 V Vin Input Voltage 0 3 7 0 V TA Operating Temperature Range 0 70 C Tstg Storage Temperature Range 55 150 C PDm Max Power Dissipation 1 5 W 68483 02 TBL With respect to VSS Stresses a...

Страница 4: ...CRT monitor The display unit consists of four hardware building blocks an TS68483 advanced graphics controller a display memory dynamic RAM a displaymemoryinterface comprising a fewTTL parts a CRT int...

Страница 5: ...lay unit This memory is addressed as four banks of 4 bit plane each BIT PLANE Each bit plane has a maximum capacityof 211 x 211 bits A byte wide organization of each bit plane is required MEMORY ADDRE...

Страница 6: ...a given type For example any drawing command may be parame tered for destination mask bit use The command code also defines the command type and its parameters A command is completely defined when a v...

Страница 7: ...not specified Xs 0 to 255 a cell dimension DXs DYs a bit plane address Zs When a character is addressed Zs gives the plane number into the bank Bs When an object is ad dressed Zs gives the source mask...

Страница 8: ...R22 R23 15 14 13 12 11 10 9 8 7 6 4 5 3 2 1 0 13 bit positive value Bank number Plane number 13 bit positive value Absolute value Absolute value 11 bit positive value 8 bit positive value Absolute va...

Страница 9: ...nerally addressed as the frame buffer When short pels are used any bank may hold a frame buffer In thiscase the bankparity selectsthe color nibble used See destination pointer section for bank address...

Страница 10: ...he penis a CELL this cell is printed at each active coordinate In the bichrome mode when the cell is a character and in the polychrome mode when the cell is an object For each active coordinates the a...

Страница 11: ...the PRINT CHARACTER PRINT OBJECT and LIN EAR commands when the pen is a cell The AREA or ACCESS or LINEAR DOT commands are never scaled The LINEAR PEN command should be used with a scaling factor of...

Страница 12: ...DXs DYs SAVE VIEWPORT Xs Ys DXs DYs MODIFY VIEWPORT Xs Ys DXs DYs These commands provide sequential access to a viewport in a frame buffer from the microprocessor data base Data are transferred to fr...

Страница 13: ...4 registers A0 selects the low order byte A0 1 or the high order byte A0 0 of the selected register A 6 7 provide the command execution condition The host microprocessor bus may be either 8 or 16 bits...

Страница 14: ...D 8 15 TS68483 TS68008 V CS R W DS CC 68483 16 EPS Figure 14 Interface with TS68000 68008MPU 37 26 28 25 29 AD 8 15 AD 0 7 A 1 7 D 0 7 D 8 15 TS68483 8086 ALE CS WR 26 28 25 29 AD 0 7 A 1 7 D 0 7 D 8...

Страница 15: ...Word 1 Long Word 1 1 Exec after 4 Bus Cycles 1 Long Word ILLEGAL Notes Word transfer must respect word boundary Long word transfer must respect long word boundary Not available with 8088 MPU type 684...

Страница 16: ...d to load the internal video RAM shift register the non displayable lines In one out of nine non displayablelines DWX cyclesare allocatedto the refresh process when it is enabled RFD 0 In Float cycle...

Страница 17: ...must be programmed to use external shift register Dummy read IV 3 4 PAN AND TILT The host can tilt or pan the Display Viewport through the frame bufferby modifying YOR or XOR arguments Panning isperfo...

Страница 18: ...the bank number X 3 10 binary value of the word address Y 0 10 binary value of the word address Z and X 0 2 are not supplied They give only a bit address in a memory word V 2 Memory Cycles 24 pins are...

Страница 19: ...onging to different banks but addressed by the same Z share a given block There is little time constraint if any One block twoZ two bit planes belongingto the same bank share a given block In this cas...

Страница 20: ...in bank3 V 3 3 OBJECTS AND CHARACTERS Objects may be located in unused parts of the frame buffer Character generators can be implemented in any plane of any bank They can also be implemented in ROM In...

Страница 21: ...rocessors UNMUX MODE Microprocessor Interface Timing A 0 7 D 0 15 AE DS CS R W VCC 5 0V 5 TA TL to TH CL 100pF on D 0 15 Reference levels VIL 0 8V and VIH 2V on all inputs VOL 0 4V and VOH 2 4V on all...

Страница 22: ...6 7 8 1 5 3 2 4 A 0 7 AS MPU CS DS R W DATA OUT D 0 15 68483 23 EPS Figure 21 Read Cycle 3 8 1 5 3 2 A 0 7 AS MPU CS DS R W DATA IN D 0 15 10 9 11 12 68483 24 EPS Figure 22 Write Cycle TS68483A 22 30...

Страница 23: ...and R W High 150 ns 6 DS Width low read 240 ns 7 R W Width low write 110 ns 8 Data Access Time From DS read 210 ns 9 Data in Set up time from R W Inactive write 150 ns 10 DS Inactive to High Impedance...

Страница 24: ...3 3 16 5 8 10 14 12 A D OUT AE CS DS R W A D 6 68483 25 EPS Figure 23 Read Cycle 1 2 4 3 3 A AE CS DS R W A D 17 5 13 15 A DIN DIN 18 9 11 11 7 FAST WRITE 68483 26 EPS Figure 24 Write Cycle TS68483A...

Страница 25: ...LK 10 ns 6 Input Data Hold Time from CLK read cycle 6 ns 7 Input Data Set up Time from CLK read cycle 10 ns 8 Input Data HI Z Time from CLK TCLK ns Note All timing is referenced to the rising edge of...

Страница 26: ...from CLK Rising Edge 30 ns 4 CLK Low Pulse Width 23 ns 5 Output Hold Time 10 ns 68483 14 TBL 2HT 7T 7T 1T 2T MARGIN MARGIN DWX FPX BKX 25LINES 25LINES 25LINES 25LINES EVEN FIELD BKY FPY DWY BPY LINES...

Страница 27: ...en Bank 0 DIB1 DIB0 MARGIN COLOR YOR XOR H BFY FPY BKY DPD VRE RFD INE BKX DWX FPX 0 MODX1 MODX0 BW MB VSIE HSIE NBLK NHVS NPC STATUS SYNC DWY DY S S DX Bd Zd S S ACW XY QF1 QF0 Bs Zs S U DXs DYs Xs Y...

Страница 28: ...CELL 10T LOOP 4T CELL 4T 10T 4T 4T see Note 1 6T 5T 4T 10T AREA MEMORY WORD EXECUTIONTIME Per DOT CELL DOT CELL MEMORY WORD MEMORY WORD DMU 1 Destination mask use SP 1 Short pel long pel when SP 0 SRU...

Страница 29: ...TEM MEMORY HOST MICROPROCESSOR DISPLAY MEMORY DISPLAYMEMORY INTERFACE TS68483 CRT CONTROLLER 4 SYNC SYNC R G B CRT INTERFACE MONITOR 8 OR 16 BITS 68483 32 EPS Figure 29 Typical Application TS68483A 29...

Страница 30: ...re not authorized for use as critical components in life support devices or systems without express written approval of SGS THOMSON Microelectronics 1994 SGS THOMSON Microelectronics All Rights Reserv...

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