LATCH
Y
2
3
B [0:1]
Y [0:2]
MUX
BANK ENABLE
CAD0
ADSEL
MEMORY
ADDRESS
64K x 8
64K x 8
8
DATA
Z0/Z2
DATA
Z1/Z3
X
ADM [8:15]
ADM [0:7]
CYCLE
CONTROLLER
RAS
CAS
OE
WE
Z1
Z1 + 2
512
384
128
BANK 0
BANK 3
64K x 8
64K x 8
SPARED AREA
One Block through Page Mode
64K x 8 MEMORY BLOCK
68483-22.EPS
Figure 20 : Memory Organization for 512 x 384 Application
VI - TIMING DIAGRAM
VI.1 - Microprocessor Interface
TS68483 has an eight bit address bus and a sixteen bit data bus. Little external logic is needed to adapt
bus control signals from most of the common multiplexed or non-multiplexed bus microprocessors.
UNMUX MODE
Microprocessor Interface Timing : A(0:7), D(0:15), AE, DS, CS, R/ W
V
CC
= 5.0V
±
5%, T
A
= T
L
to T
H
, C
L
= 100pF on D(0:15)
Reference levels : V
IL
= 0.8V and V
IH
= 2V on all inputs, V
OL
= 0.4V and V
OH
= 2.4V on all outputs
Indent Number
Parameter
Min.
Max.
Unit
1
Address Set up Time from CS
0
ns
2
Data Strobe Width (high)
65
ns
3
AS Set up Time from CS
0
ns
4
Data Strobe Width-low (read cycle)
160
ns
5
Address Hold Time from DS
0
ns
6
Data Access time from CS (read cycle)
130
ns
7
DS Inactive to High Impedance State (read cycle)
10
80
ns
8
R/W Set up Time from DS
20
ns
9
DS Width-low (write cycle)
80
ns
10
CS Set up Time from DS Active (write Cycle)
0
ns
11
Data in Set up Time from DS active (write cycle)
10
ns
12
Data in Hold Time from DS Inactive (write cycle)
15
ns
68483-11.TBL
TS68483A
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