11-18
Testing and Troubleshooting
Date Code 20010731
SEL-352-1, -2 Instruction Manual
2. Connect an external timer and set it to start when the TRIPA input asserts and stop
when the programmable output you set in Step 1 asserts.
3. Apply A-phase current above the 50FT setting.
4. Assert the TRIPA input. This action causes the relay to start its 62FC timer. The
external timer should also start.
5. Shortly after the TRIPA input asserts, the programmable output contact set in
Step 1 should close, indicating FBF bit assertion. This action should stop the
external timer. Record the timer reading. It should be close to the FCpu timer
setting.
6. Shut off A-phase current.
7. Deassert the TRIPA input.
8. This step is optional. To test Scheme 1 logic operation under conditions that
could represent normal relay/breaker operation, repeat Steps 3 and 4. This time,
turn off A-phase current 1.5 to 2.0 cycles before the 62FC timer expires. The FBF
bit should not assert.
9. Repeat Steps 3, 4, 5, 6, 7, and 8 (optional) for phases B and C.
10. Assert the TRIPA input. This action should start the external timer.
11. Quickly apply A-phase current above the 50FT setting. When the TRIPA input is
asserted before A-phase current is applied, A-phase current must be applied before
the 62TTdo timer expires. This sequence simulates relay operation when used in
a ring-bus application.
12. Shortly after applying current to the A-phase, the programmable output contact set
in Step 1 should close, indicating FBF bit assertion. This action should stop the
external timer. Record the timer reading. It should be close to the FCpu timer
setting.
13. Deassert the TRIPA input and shut off A-phase current.
14. This step is optional. To test Scheme 1 logic operation under conditions that
could represent normal relay/breaker operation, repeat Steps 9 and 10. This time,
turn off A-phase current 1.5 to 2.0 cycles before the 62FC timer expires. The FBF
bit should not assert.
15. Repeat Steps 9, 10, 11, 12, 13, and 14 (optional) for phases B and C.
16. For each test, the relay generated a sequential events record for the elements
programmed in Step 1. View the SER using the
SER
command. These time
stamps will also verify the TTdo and FCpu timers. The TTdo timer is the time the
FBF bit remains asserted after the TRIPA input was deasserted.
Содержание SEL-352-1
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