
7-16
Inputs, Outputs, Timers, and Other Control Logic
Date Code 20011205
SEL-311A Instruction Manual
Figure 7.14: Latch Control Switch Operation Time Line
Latch Control Switch States Retained
Power Loss
The states of the latch bits (LT1 through LT16) are retained if power to the relay is lost and then
restored. If a latch bit is asserted (e.g., LT2 = logical 1) when power is lost, it comes back
asserted (LT2 = logical 1) when power is restored. If a latch bit is deasserted (e.g., LT3 =
logical 0) when power is lost, it comes back deasserted (LT3 = logical 0) when power is restored.
This feature makes the latch bit feature behave the same as traditional latching relays. In a
traditional installation, if power is lost to the panel, the latching relay output contact position
remains unchanged.
Note:
Although the relay retains the state of a latched bit when power is cycled, the relay
cannot hold output contact closure when power is removed from the relay (output
contacts go to their deenergized states).
Settings Change or Active Setting Group Change
If individual settings are changed (for the active setting group or one of the other setting groups)
or the active setting group is changed, the states of the latch bits (Relay Word bits LT1 through
LT16) are retained, much like in the preceding “Power Loss” explanation.
If individual settings are changed for a setting group other than the active setting group, there is
no interruption of the latch bits (the relay is not momentarily disabled).
Содержание SEL-311A
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