The two registers shown below are standard PC registers important for NMI handling.
7
6
5
4
3
2
1
0
PORT061
IOCH
ENIOC
I/O
Port at $061, PC/AT compatible
$061
R/W
IOCH
IOCHCK state. This bit reflects the latched state of the IOCHCK line of the ISA
bus. If the IOCHCK line is asserted, this bit will be set.
ENIOC
Enable IOCHCK. This bit enables the IOCHCK line. If this bit is cleared and
the NMI is enabled via the RTC, an active IOCHCK line issues an NMI.
7
6
5
4
3
2
1
0
RTCADD
NMIM
I/O
RTC Address Register
$070
W
NMIM
NMI Mask bit. When this bit is set the NMI is disabled. When cleared, the NMI
function is enabled and the IOCHCK line can trigger an NMI. Note that
RTCADD is a write-only register. BIOS calls (also via DOS call) and
application software accessing the CMOS RAM may change the NMIM bit.
3.11.5
Reset Button
The lever switch on the front panel has two functions. Pushing the lever to the upwards will issue a
reset, while pushing downwards will trigger a NMI.
The reset signal is active for all subsystems of the VP7.
3.11.6
Speaker
A standard PC compatible speaker is onboard. An external standard PC compatible speaker may be
connected between the appropriate IO connector at the back side and +5V.
The register shown below is a standard PC register used for speaker programming.
7
6
5
4
3
2
1
0
PORT061
TIM2_OUT
SPK_DAT
SPK_GAT
I/O
Port at $061, PC/AT compatible
$061
R/W
TIM2_OUT
R
Timer channel 2 out. Toggles with the frequency defined by timer 2 when
SPK_GAT is set.
SPK_DAT
Speaker data. When set, the speaker is fed with a frequency defined by
timer 2. SPK_GAT must be set before.
SPK_GAT
Speaker gate. Enable timer 2 gate to speaker.
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