3
Function Blocks
3.1
Standard AT-Devices
3.1.1
DMA Controller
In standard AT compatible PCs, as well as on the VP7 two DMA controllers integrated on the board are
internally cascaded. Both controllers are compatible with the Intel 8237A. The DMA Controller 1
(DMAC1) is used for byte-wide transfers while the DMAC2 is used for word-wide transfers.
3.1.2
Interrupt Controller
The Interrupt controller on a standard PC consists of two 82C59A devices with eight interrupt request
lines each. The two controllers are cascaded to provide 14 external and two internal interrupt sources.
The master interrupt controller provides IRQ[7..1] and the slave interrupt controller provides
IRQ[15..8]. IRQ2 is used to cascade the two controllers, IRQ0 is used as a system timer interrupt and is
tied to interval timer 1, counter 0. The remaining 14 interrupt lines are mapped to various onboard
devices.
Each 82C59A provides several internal registers. The interrupts at the IRQ input lines are handled by
two registers, the interrupt request register IRR and the in-service register ISR. For programming details
see the 82C59A data sheet.
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