3.10
VMEbus Interface
The VP7 contains the UNIVERSE VMEbus interface chip. It contains a complete high performance 64-
bit VMEbus interface with 32-bit PCI master/slave capability. Furthermore a system controller is
implemented to allow the VP7 to reside in slot 1 without the necessity of an extra system controller.
Slot 1 auto detection may be overridden by Setup.
Universe Register
All of the controlling registers are located in the UNIVERSE. The registers are memory mapped and
after Power-On the base address is assigned dynamically by BIOS. 4 Kbytes address space are reserved
for these registers.
Universe PCIbus Address Space
By default the VMEbus interface is disabled. If the VP7 needs to access the VMEbus, the VMEbus logic
must be enabled and the PCI address spaces must be defined. Multiple PCI to VMEbus address space
mappings with different attributes (A16, A24, D16, D32, User, ...) are possible. The size of available
address space can be adjusted by BIOS Setup.
Universe VMEbus Address Space
VMEbus address space may be defined when another VMEbus master needs to access internal memory.
Any location accessible over the PCIbus can be used.
Local Interrupt
UNIVERSE Interrupt line LINT 0 may be assigned by BIOS to a local interrupt line. Interrupt sharing
with other PCI devices may be allowed when all interrupt lines support level driven mode (typical for
PCI devices) and all interrupt service handlers know of this feature. The other seven interrupt lines
LINT 1 .. LINT 7 are not connected.
The driver software (onboard SCSI and Ethernet controller) of the most common operating
systems, support interrupt sharing.
Features
•
Fully compliant, 32-bit, 33 MHz PCI local bus interface
•
fully compliant, high performance 64-bit VMEbus interface
•
integral FIFOs for write posting to maximise bandwidth utilisation
•
programmable DMA controller with linked list support
•
VMEbus transfer rates of 60-70 Mbytes/sec
•
complete suite of VMEbus address and transfer modes
•
A32/A24/A16 master and slave
•
D64 (MBLT)/D32/D16/D8 master and slave
•
BLT, ADOH, RMW, LOCK
•
flexible register set, programmable from both the PCI and VMEbus ports
•
full VMEbus system controller functionality
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