2.6
Jumper Configuration
The only user accessible jumper of the VP7 is J7301. This jumper defines the strategy for VME bus
resets.
J7301 1-2
VME bus reset (SYSRES*) generated only when Universe chip is setup for VME bus
system controller. If the VP7 is not set as system controller, a reset will only affect on
the VP7 board.
In this setting the SYSRES* signal has no steady state at low state. During
pressed reset button the SYSRES* is inactive after releasing of the reset button
the reset line will toggle for 270ms with a frequency of 1MHz. This is caused by
the Universe chip. Please check if the used VME cards can tolerate such
SYSRES* signal waveform.
J7301 2-3
VME bus reset is generated by Power On or Reset button (factory default setting).
J7301 open
VME bus reset is never generated.
System controller:
As specified by the VME64 specification the First Slot Detector module on the Universe VME
controller samples BG3IN* immediately after reset to determine whether the Universe’s host board
resides in slot 1. The VMEbus specification requires that BG[3:0]* lines be driven high after reset. This
means that if a card is preceded by another card in the VMEbus system, it will always sample BG3IN*
high after reset. BG3IN* can only be sampled low after reset by the first card in the system (there is no
preceding card to drive BG3IN* high). If BG3IN* is sampled at logic low immediately after reset (due
to the Universe’s internal pull-down), then the Universe’s host board is in slot 1 and the Universe
becomes system controller. This mechanism may be overridden by the system BIOS setup.
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