3.11.1.2
Serial EEPROM
For storage of user data a serial EEPROM is implemented on the VP7 board. It is a standard 24C04 type
EEPROM with 512 bytes. More information about writing and reading the contents can be found in the
datasheets from the manufacturer (e.g. Microchip Technology, SGS Thomson, Atmel, Catalyst and
many others).
3.11.2
Watchdog, Powerfail Monitor
For security of application software, the VP7 offers a software controlled hardware watchdog capable of
issuing a reset signal if its time-out interval expires. To prevent the watchdog from generating a reset
signal, it must be re-triggered within a 0.5 second interval by reading the Watchdog Control Register
WCR.
Since standard software doesn't trigger the watchdog periodically, it is disabled after reset.
The watchdog
function can be enabled via the Watchdog Control Register WCR. If the watchdog is enabled, it must be
reset periodically by reading WCR within 0.5 seconds. Otherwise, a reset pulse with a duration of 200msec
is generated to restart the system. A watchdog reset which has occurred and reset the system can be
detected by monitoring the WDG_REL line and the state of the WCR register bit 2.
15
..
..
4
3
2
1
0
WCR
WD_RES
WD_SET
WD_ON
I/O
Watchdog Control Register
reset:
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power down/up:
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R/W
WD_ON
Watchdog Enable. When this bit is set, the watchdog function is enabled,
otherwise it is disabled. To prevent a reset generated by the enabled watchdog
circuit, it must be re-triggered by reading the WCR. This bit is readable. This
bit is set to 1 by a System Reset.
WD_SET
When set to 1, this bit sets the Watchdog output line directly. This bit is not readable. This
bit is reset to 0 by a System Reset.
WD_RES
When set to 1, this bit resets the watchdog flip flop. The watchdog flip flop is not reset by a
system Reset. The watchdog flip flop is reset by a power down/up cycle. This bit is readable.
Reading this bit gives the current state of the WDG_REL line. Software can determine
whether the last System Reset was caused by the watchdog by reading this bit. If a 1 is read,
the last Reset was caused by the watchdog.
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