SH7262/SH7264 Group
Hardware Design Guide
REJ06B0999-0100 Rev. 1.00
Page 29 of 36
Jun. 30, 2010
9.1 Sleep
Mode
In sleep mode, only CPU stops its operation.
When executing the SLEEP instruction while the STBY bit in the Standby control register 1 (STBCR1) is 0, the
SH7264 transitions from the program execution state to sleep mode. The CPU stops its operation immediately after
executing the SLEEP instruction; however internal register values remain unchanged, and on-chip peripherals continue
to operate in sleep mode. The CKIO pin continues to output clock pulses.
9.2 Software
Standby
Mode
The SH7264 stops its operation completely in software standby mode.
When executing the SLEEP instruction while the STBY bit in the STBCR1 is 1, and DEEP bit is 0, the SH7264
transitions from the program execution state to software standby mode. Not only the CPU, but the clock and on-chip
peripherals stop operation in software standby mode. In addition, the CKIO pin stops outputting clock pulses.
CPU and Cache register values are retained in software standby mode. Some on-chip registers are initialized.
The CPU writes data in STBCR1 in a cycle and executes the next instruction. However, it takes one or more cycles to
actually write data in the register. Therefore, execute the SLEEP instruction after reading STBCR1 to reflect the write
value from CPU to STBCR1 in the SLEEP instruction.
9.3
Deep Standby Mode
Deep standby mode stops the SH7264 completely and turns OFF the SH7264.
When executing the SLEEP instruction while the bits STBY and DEEP in STBCR1 is 1, the SH7264 transitions from
the program execution state to deep standby mode. Not only the CPU, clock, and on-chip peripheral modules stop
operation, but all modules are off, other than the data-retention internal RAM which is set by bits RRAMKP3 to
RRAMKP0 in the On-chip data-retention RAM area setting register (RRAMKP) to reduce the power consumption
substantially. Therefore, CPU and cache register values, and on-chip peripheral module register values are not retained.
Pin states are retained just before transition to deep standby mode.
The CPU writes data in Deep standby cancel source flag register (DSFR) in a cycle and executes the next instruction.
However, it takes one or more cycles to actually write data in the register. Therefore, execute the SLEEP instruction
after reading the DSFR to reflect the write value from CPU to the DSFR in the SLEEP instruction.
For more information about deep standby mode, refer to the application note "SH7262 Group, SH7264 Group Using
Deep Standby Mode in Power-down Mode".
9.4 Module
Standby Function
The module standby function stops on-chip peripherals separately.
Set the MSTP bits in the Standby control registers of each module to 1 to stop supplying clock to the corresponding on-
chip peripherals. The power consumption is reduced in power execution state and sleep mode by this function. Make
sure to disable a module before setting it in module standby mode. Do not access the registers of a module in module
standby mode.
