SH7262/SH7264 Group
Hardware Design Guide
REJ06B0999-0100 Rev. 1.00
Page 26 of 36
Jun. 30, 2010
7. On-chip Resource Access
The SH7264 includes the high-speed internal RAM, large-capacity internal RAM, and on-chip peripheral modules as
the on-chip resources. The number of cycles to access the high-speed internal RAM varies according to the bus used.
For details on buses connected to on-chip resources, refer to Figure 1.3 Block Diagram in the SH7262 Group, SH7264
Group Hardware Manual.
Table 10 lists the number of cycles for access to the on-chip resources.
Table 10 Number of Cycles for Access to the On-chip Resources
High-speed internal RAM
(1)
Internal DMA bus (ID bus)
Read/
Write
CPU
instruction
fetch bus
(F bus)
CPU memory
access bus
(M bus)
I
φ
:B
φ
clock ratio
Number of
cycles to
access
Large-capacity
internal RAM
(1)
Internal
peripheral
register
1:1 3
B
φ
2:1 2
B
φ
3:1 2
B
φ
4:1 2
B
φ
6:1 1
B
φ
Read 1
I
φ
1
I
φ
8:1 1
B
φ
1 B
φ
2 or more P
φ
1:1 2
B
φ
2:1 2
B
φ
3:1 2
B
φ
4:1 2
B
φ
6:1 1
B
φ
Write 1
I
φ
1
I
φ
8:1 1
B
φ
1 B
φ
2 or more P
φ
Note: The High-speed internal RAM and large-capacity internal RAM are composed of several pages, and
each page has a port for reading/writing. Periherals may access various RAM pages simultaneously,
conflict only occurs when accessing the same page from several buses at the same time, causing
some degradation in the RAM performance. This is easily avoided in software by partitioning RAM
usage and buffers to avoid that situation (i.e. peripherals accessing the RAM access different pages).
A very simple example might be don’t put the stack (high usage memory) in the same memory page
where you are capturing video or in a high usage Ethernet buffer and thus avoid “collisions”.
