SH7262/SH7264 Group
Hardware Design Guide
REJ06B0999-0100 Rev. 1.00
Page 7 of 36
Jun. 30, 2010
2. Reset
2.1 Power-on/Power-off
Sequence
Either the 1.2 V power supplies (Vcc, PLVcc, USBAVcc, USBDVcc, and USBUVcc) or 3.3 V power supplies (PVcc,
AVcc, USBAPVcc, and USBDPVcc) can be turned ON or OFF first.
When turning ON the SH7264, make sure to fix pins TRST# and RES# to low level. If not, output pins and I/O pins
(output) may be in undefined state to cause malfunction in the entire system.
To avoid such malfunction described above, make sure to fix pins TRST# and RES# to low level when turning OFF the
SH7264.
2.2
Oscillation Settling Time
When the RES# pin is driven low, the SH7264 enters the power-on reset state. To make sure to reset the SH7264, the
RES# pin must be kept at the low level during the oscillation settling time at power-on, or when exiting from software
standby mode and deep standby mode. Keep the RES# pin at low level for at least 20 t
cyc
when setting the RES# pin to
low level while the clock is running.
The power-on oscillation settling time (t
osc1
) is 10 ms, which is specified from when the Vcc exceeds the minimum
operating voltage until the RES# pin exceeds the V
IL
voltage. Figure 4 shows the relation between power-on/off and
clock, reset signals. This timing is easily accommodated by many "supervisor" ICs available on the market such as
Renesas Electronics RNA51957BFP.
CKIO,
Internal clock
Vcc
RES#
TRST#
Vcc Min.
Power-on oscillation settling time (t
OSC1
)
Stability oscillation period
Vcc Min.
Normal operation period
(Instruction processing)
Note: Oscillation settling time when the internal oscillator is used.
MD_BOOT1
MD_BOOT0
MD_CLK1
MD_CLK0
Mode hold time (t
MDH
)
Figure 4 Relations between Power-on/off and Clock, Reset Signals
