SH7262/SH7264 Group
Hardware Design Guide
REJ06B0999-0100 Rev. 1.00
Page 8 of 36
Jun. 30, 2010
2.3 Power-on
Reset
The SH7264 has two reset options; power-on reset and manual reset. This section describes sources for the power-on
reset exception handling.
2.3.1
Power-on Reset by the RES# Pin
When the RES# pin is driven low, the SH7264 enters power-on reset state to initialize the CPU’s internal state and all
on-chip peripheral registers
(note)
. In power-on reset state, power-on reset exception handling starts when the RES# pin is
first driven low for a fixed period and then returns to high. For more information on the "fixed period" to drive the
RES# pin low, refer to 2.2 Oscillation Settling Time.
2.3.2
Power-on Reset by the User Debug Interface (H-UDI) Reset Assert Command
When the H-UDI reset assert command is set, the SH7264 enters the power-on reset state to initialize the CPU’s
internal state and all on-chip peripheral registers
(note)
, like the power-on reset by the RES# pin. Power-on reset
exception handling starts in power-on reset state. The period required between the H-UDI reset assert command and the
H-UDI reset negate command is the same as the period to drive the RES# pin low to start the power-on reset.
2.3.3
Power-on Reset by the Watchdog Timer (WDT)
When setting the WDT as watchdog timer mode, and specifying the power-on reset when the WDT watchdog timer
counter (WTCNT) overflows, the SH7264 enters power-on reset state and the WDT starts power-on reset exception
handling, however, the Watchdog reset control/status register (WRCSR) of the WDT and the Frequency control register
(FRQCR) of the Clock Pulse Generator (CPG) are not initialized
(note)
.
Note: For more information on register status, refer to 36.3 Register States in Each Operating Mode in the SH7262
Group, SH7264 Group Hardware Manual.
2.4 Manual
Reset
This section describes sources for the manual reset exception handling.
2.4.1
Manual Reset by the Watchdog Timer (WDT)
When setting the WDT as watchdog timer mode, and specifying the manual reset when the WTCNT of the WDT
overflows, the SH7264 enters manual reset state and the WDT starts manual reset exception handling.
When the SH7264 enters manual reset state while the CPU is leaving the bus or the Direct Memory Access Controller
(DMAC) transfers data in burst mode, the manual reset exception handling is deferred until the CPU retrieves the bus.
In manual reset state, the SH7264 initializes CPU and the BN bit in the Bank number register (IBNR) of the Interrupt
controller (INTC), but FPU and other modules are not included
(note)
.
Note: For more information on register status, refer to 36.3 Register States in Each Operating Mode in the SH7262
Group, SH7264 Group Hardware Manual.
2.5
System Reset by the Watchdog Timer (WDT)
Sometimes it is desirable to have the WDT reset the entire system during an overflow condition using the WDTOVF#
signal from the WDT. In this case the WDTOVF# should be not be connected directly to the RES# of the MCU as this
would cause problems. A “tiny” gate can be used to OR the “power-on” reset signal and the WDTOVF# as shown in
Figure 5: System Reset using WDTOVF#.
