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16.2
Register Descriptions
16.2.1
A/D Data Register A–D (ADDRA0–ADDRD0, ADDRA1–ADDRD1)
A/D registers are special registers that read stored results of A/D conversion in 16 bits. There are
eight registers: ADDRA0–ADDRD0 (A/D0) and ADDRA1–ADDRD1 (A/D1).
The A/D converted data is 10 bit data which is to the ADDR of the corresponding converted
channel for storage. The upper 8 bits of the A/D converted data correspond to the upper byte of the
ADDR and the lower 2 bits correspond to the lower byte. Bits 5–0 of the lower byte of ADDR are
reserved and always read 0. Analog input channels and correspondence to ADDR are shown in
table 16.3.
ADDR can always be read from the CPU. The upper byte may be read directly. The lower byte is
transferred through the temporary register (TEMP). For details, see section 16.3, Interface with
CPU.
ADDR is initialized to H'0000 during power-on reset or standby mode. ADDR will not be
initialized by manual reset.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
ADDRn :
R/W :
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
(n=A to D)
Initial value :
Bit :
Table 16.3
Analog Input Channel and ADDRA–ADDRD Correspondence
Analog Input Channel
A/D Data Register
Module
AN0
ADDRA0
A/D0
AN1
ADDRB0
AN2
ADDRC0
AN3
ADDRD0
AN4
ADDRA1
A/D1
AN5
ADDRB1
AN6
ADDRC1
AN7
ADDRD1
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