Renesas SH7041 Series, Руководство по оборудованию, Страница: 351 / 923

313
12.2.7 Timer General Register (TGR)
Each timer general register (TGR) is a 16-bit register that can function as either an output compare
register or an input capture register. There are a total of sixteen TGR, four each for channels 0, 3,
and 4, and two each for channels 1 and 2. The TGRC and TGRD of channels 0, 3, and 4 can be set
to operate as buffer registers. The TGR register and buffer register combinations are TGRA with
TGRC, and TGRB with TGRD.
The TGRs are initialized to H'FFFF by a power-on reset or in standby mode. Manual reset does
not initialize TGR. Accessing of the TGRs in 8-bit units is disabled; they may only be accessed in
16-bit units.
Bit: 15 14 13 12 11 10 9 8
Initial value: 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
Initial value: 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
12.2.8 Timer Start Register (TSTR)
The timer start register (TSTR) is an 8-bit read/write register that starts and stops the timer
counters (TCNT) of channels 0–4. TSTR is initialized to H'00 upon power-on reset or standby
mode. Manual reset does not initialize TSTR.
Bit: 7 6 5 4 3 2 1 0
CST4 CST3 — — — CST2 CST1 CST0
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R R R R/W R/W R/W
•
Bits 7, 6, 2–0—Counter Start 4–0 (CST4–CST0): Select the start and stop of the timer counters
(TCNT). The counter start to channel and bit to channel correspondence are indicated in the
tables below.