Renesas SH7041 Series, Руководство по оборудованию, Страница: 197 / 923

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Table 9.2 Special Cache Space
Space Classification Address Size Bus Width
Address array H'FFFFF000–H'FFFFF3FF 1 kbyte 32 bit
Data array H'FFFFF400–H'FFFFF7FF 1 kbyte 32 bit
9.3.1 Cache Address Array Read/Write Space
The cache address array has a compulsory read/write (figure 9.3).
Address
Upper 22 bits of the address array space address
(22 bits)
–
(2 bits)
Entry address
(8 bits)
31 0 2 1 10 9
Data
–
(6 bits)
–
(10 bits)
Tag address
(15 bits)
Valid bit (1 bit)
31 0 10 9 26 25 24
Figure 9.3 Cache Address Array
Address Array Read: Designates entry address and reads out the corresponding tag address
value/valid bit value.
Address Array Write: Designates entry address and writes the designated tag address value/valid
bit value.
9.3.2 Cache Data Array Read/Write Space
The cache data array has a compulsory read/write (figure 9.4).
Address
Upper 22 bits of the data array space address
(22 bits)
–
(2 bits)
Entry address
(8 bits)
31 0 2 1 10 9
Data
Data
(32 bits)
31 0
Figure 9.4 Cache Data Array
Data Array Read: Designates entry address and reads out the corresponding line of data.
Data Array Write: Designates entry address and writes designated data to the corresponding line.