Renesas SH7041 Series, Руководство по оборудованию, Страница: 228 / 923

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10.4.2 Basic Timing
The SH7040 Series supports 2 CAS format DRAM access. The DRAM access basic timing is a
minimum of 3 cycles for normal mode. Figure 10.7 shows the basic DRAM access timing. DRAM
space access is controlled by
RAS
,
CASx
, and RDWR signals. The following signals are
associated with transfer of these actual byte locations:
CASHH
(bits 31–24),
CASHL
(bits 23–16),
CASH
(bits 15–8), and
CASL
(bits 7–0). However, the signals for ordinary space,
WRx
and
RD,
are also output during the DMAC single transfer column address cycle period. T
p
is the precharge
cycle, T
r
is the RAS assert cycle, T
c
is the CAS assert cycle and T
c2
is the read data fetch cycle.
T
p
T
r
T
c1
T
c2
CK
Write
Read
Address
Data
RAS
CASx
RDWR
Data
RDWR
CASx
RAS
Row Column
Figure 10.7 DRAM Bus Cycle (Normal Mode, TPC = 0, RCD = 0, No Waits)