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ix
13.1 Overview............................................................................................................................ 455
13.1.1 Features................................................................................................................. 455
13.1.2 Block Diagram...................................................................................................... 456
13.1.3 Pin Configuration ................................................................................................. 456
13.1.4 Register Configuration ......................................................................................... 457
13.2 Register Descriptions......................................................................................................... 457
13.2.1 Timer Counter (TCNT)......................................................................................... 457
13.2.2 Timer Control/Status Register (TCSR) ................................................................ 458
13.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 460
13.2.4 Register Access..................................................................................................... 461
13.3 Operation ........................................................................................................................... 462
13.3.1 Watchdog Timer Mode......................................................................................... 462
13.3.2 Interval Timer Mode............................................................................................. 464
13.3.3 Clearing the Standby Mode .................................................................................. 464
13.3.4 Timing of Setting the Overflow Flag (OVF)........................................................ 465
13.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF) ........................ 465
13.4 Notes on Use ...................................................................................................................... 466
13.4.1 TCNT Write and Increment Contention............................................................... 466
13.4.2 Changing CKS2–CKS0 Bit Values ...................................................................... 466
13.4.3 Changing between Watchdog Timer/Interval Timer Modes ................................ 466
13.4.4 System Reset With
WDTOVF
............................................................................. 467
13.4.5 Internal Reset with the Watchdog Timer.............................................................. 467
Section 14 Serial Communication Interface (SCI)
..................................................... 469
14.1 Overview............................................................................................................................ 469
14.1.1 Features................................................................................................................. 469
14.1.2 Block Diagram...................................................................................................... 470
14.1.3 Pin Configuration ................................................................................................. 471
14.1.4 Register Configuration ......................................................................................... 471
14.2 Register Descriptions......................................................................................................... 472
14.2.1 Receive Shift Register (RSR) ............................................................................... 472
14.2.2 Receive Data Register (RDR)............................................................................... 472
14.2.3 Transmit Shift Register (TSR).............................................................................. 472
14.2.4 Transmit Data Register (TDR) ............................................................................ 473
14.2.5 Serial Mode Register (SMR) ................................................................................ 473
14.2.6 Serial Control Register (SCR) .............................................................................. 476
14.2.7 Serial Status Register (SSR) ................................................................................. 479
14.2.8 Bit Rate Register (BRR) ....................................................................................... 483
14.3 Operation ........................................................................................................................... 501
14.3.1 Overview............................................................................................................... 501
14.3.2 Operation in Asynchronous Mode........................................................................ 503
14.3.3 Multiprocessor Communication ........................................................................... 513
14.3.4 Clock Synchronous Operation.............................................................................. 521
Содержание SH7041 Series
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