7542 Group
Rev.3.02 Oct 31, 2006 Page 47 of 134
REJ03B0006-0302
Fig. 54 Block diagram of UART serial I/O1
(2) Asynchronous Serial I/O1 (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit of the serial I/O1 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Fig. 55 Operation of UART serial I/O1 function
X
I
N
1/4
OE
PE FE
1/16
1
/
1
6
D
a
t
a
b
u
s
R
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
1
A
d
d
r
e
s
s
0
0
1
8
1
6
R
e
c
e
i
v
e
s
h
i
f
t
r
e
g
i
s
t
e
r
1
R
e
c
e
i
v
e
b
u
f
f
e
r
f
u
l
l
f
l
a
g
(
R
B
F
)
R
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
(
R
I
)
Baud rate generator 1
F
r
e
q
u
e
n
c
y
d
i
v
i
s
i
o
n
r
a
t
i
o
1
/
(
n
+
1
)
A
d
d
r
e
s
s
0
0
1
C
1
6
S
T
/
S
P
/
P
A
g
e
n
e
r
a
t
o
r
Transmit buffer register 1
Data bus
T
r
a
n
s
m
i
t
s
h
i
f
t
r
e
g
i
s
t
e
r
1
Address
0018
16
Transmit shift completion flag (TSC)
T
r
a
n
s
m
i
t
b
u
f
f
e
r
e
m
p
t
y
f
l
a
g
(
T
B
E
)
T
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
(
T
I
)
Address
0019
16
ST detector
SP detector
U
A
R
T
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
Address 001B
16
Character length selection bit
A
d
d
r
e
s
s
0
0
1
A
1
6
B
R
G
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
Transmit interrupt source selection bit
S
e
r
i
a
l
I
/
O
1
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
C
l
o
c
k
c
o
n
t
r
o
l
c
i
r
c
u
i
t
C
h
a
r
a
c
t
e
r
l
e
n
g
t
h
s
e
l
e
c
t
i
o
n
b
i
t
7
b
i
t
s
8
b
i
t
s
S
e
r
i
a
l
I
/
O
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
P
1
2
/
S
C
L
K
1
Serial I/O1 status register
P
1
0
/
R
X
D
1
/
C
A
P
0
P1
1
/T
X
D
1
TSC=0
TBE=1
RBF=0
TBE=0
TBE=0
RBF=1
RBF=1
ST
D
0
D
1
SP
D
0
D
1
ST
SP
TBE=1
TSC=1
ST
D
0
D
1
SP
D
0
D
1
ST
SP
Transmit or receive clock
Transmit buffer 1
write signal
Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Notes
✽
✽
Serial output T
X
D
1
Serial input R
X
D
1
Receive buffer 1
read signal