7542 Group
Rev.3.02 Oct 31, 2006 Page 101 of 134
REJ03B0006-0302
Timing Requirements (General purpose)
Table 22 Timing requirements (1) (General purpose)
(FLASH ROM version: V
CC
= 4.0 to 5.5V, Mask ROM version: V
CC
= 4.0 to 5.5 V, V
SS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min.
Typ.
Max.
Symbol
Parameter
Limits
Unit
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR
0
input cycle time
CNTR
0
, INT
0
, INT
1
, CAP
0
, CAP
1
input “H” pulse width (Note 1)
CNTR
0
, INT
0
, INT
1
, CAP
0
, CAP
1
input “L” pulse width (Note 1)
Serial I/O1, serial I/O2 clock input cycle time (Note 2)
Serial I/O1, serial I/O2 clock input “H” pulse width (Note 2)
Serial I/O1, serial I/O2 clock input “L” pulse width (Note 2)
Serial I/O1, serial I/O2 input set up time
Serial I/O1, serial I/O2 input hold time
t
W
(RESET)
t
C
(X
IN
)
t
WH
(X
IN
)
t
WL
(X
IN
)
t
C
(CNTR
0
)
t
WH
(CNTR
0
)
t
WL
(CNTR
0
)
t
C
(S
CLK1
)
t
WH
(S
CLK1
)
t
WL
(S
CLK1
)
t
su
(RxD
1
–S
CLK1
)
t
h
(S
CLK1
–RxD
1
)
2
125
50
50
200
80
80
800
370
370
220
100
µ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 23 Timing requirements (2) (General purpose)
(FLASH ROM version: V
CC
= 2.7 to 5.5V, Mask ROM version: V
CC
= 2.4 to 5.5 V, V
SS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min.
Typ.
Max.
Symbol
Parameter
Limits
Unit
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR
0
input cycle time
CNTR
0
, INT
0
, INT
1
, CAP
0
, CAP
1
input “H” pulse width (Note 1)
CNTR
0
, INT
0
, INT
1
, CAP
0
, CAP
1
input “L” pulse width (Note 1)
Serial I/O1, serial I/O2 clock input cycle time (Note 2)
Serial I/O1, serial I/O2 clock input “H” pulse width (Note 2)
Serial I/O1, serial I/O2 clock input “L” pulse width (Note 2)
Serial I/O1, serial I/O2 input set up time
Serial I/O1, serial I/O2 input hold time
t
W
(RESET)
t
C
(X
IN
)
t
WH
(X
IN
)
t
WL
(X
IN
)
t
C
(CNTR
0
)
t
WH
(CNTR
0
)
t
WL
(CNTR
0
)
t
C
(S
CLK1
)
t
WH
(S
CLK1
)
t
WL
(S
CLK1
)
t
su
(RxD
1
–S
CLK1
)
t
h
(S
CLK1
–RxD
1
)
2
250
100
100
500
230
230
2000
950
950
400
200
µ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: As for CAP
0
, CAP
1
, it is the value when noise filter is not used.
2: In this time, bit 6 of the serial I/O1 control register (address 001A
16
) is set to “1” (clock synchronous serial I/O is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.
In this time, bit 6 of the serial I/O2 control register (address 0030
16
) is set to “1” (clock synchronous serial I/O is selected).
When bit 6 of the serial I/O2 control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.
Notes 1: As for CAP
0
, CAP
1
, it is the value when noise filter is not used.
2: In this time, bit 6 of the serial I/O1 control register (address 001A
16
) is set to “1” (clock synchronous serial I/O is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
In this time, bit 6 of the serial I/O2 control register (address 0030
16
) is set to “1” (clock synchronous serial I/O is selected).
When bit 6 of the serial I/O2 control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.