7542 Group
Rev.3.02 Oct 31, 2006 Page 19 of 134
REJ03B0006-0302
I/O Ports
[Direction registers] PiD
The I/O ports have direction registers which determine the input/
output direction of each pin. Each bit in a direction register corre-
sponds to one pin, and each pin can be set to be input or output.
When “1” is set to the bit corresponding to a pin, this pin becomes
an output port. When “0” is set to the bit, the pin becomes an in-
put port.
When data is read from a pin set to output, not the value of the pin
itself but the value of port latch is read. Pins set to input are float-
ing, and permit reading pin values.
If a pin set to input is written to, only the port latch is written to and
the pin remains floating.
Note: P2
6
/AN
6
, P2
7
/AN
7
, P3
5
and P3
6
do not exist for the 32-pin version
and PWQN0036KA-A package.
Accordingly, the following settings are required;
• Select P3
3
for the INT
1
function.
• Set direction registers of ports P2
6
and P2
7
to output.
• Set direction registers of ports P3
5
and P3
6
to output.
[Port P0P3 drive capacity control register] DCCR
By setting the Port P0P3 drive capacity control register (address
0015
16
), the drive capacity of the N-channel output transistor for
the port P0 and port P3 can be selected.
[Pull-up control register] PULL
By setting the pull-up control register (address 0016
16
), ports P0
and P3 can exert pull-up control by program. However, pins set to
output are disconnected from this control and cannot exert pull-up
control.
[Port P1P3 control register] P1P3C
By setting the port P1P3 control register (address 0017
16
), a
CMOS input level or a TTL input level can be selected for ports
P1
0
, P1
2
, P1
3
, P3
6
, and P3
7
by program.
Fig. 19 Structure of port P1P3 control register
Fig. 18 Structure of pull-up control register
Port P1P3 control register
(P1P3C: address 0017
16
, initial value: 00
16
)
b7 b0
Note: Keep setting the P3
6
/INT
1
input level selection bit
to “0” (initial value) for 32-pin version and 36PJW-A package.
Not used
1 : TTL level
0 : CMOS level
P1
0
,P1
2
,P1
3
input level selection bit
1 : TTL level
0 : CMOS level
P3
6
/INT
1
input level selection bit
1 : TTL level
0 : CMOS level
P3
7
/INT
0
input level selection bit
Pull-up control register
(PULL: address 0016
16
, initial value: 00
16
)
P
0
0
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
P
0
1
,
P
0
2
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
P
0
3
–P
0
7
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
P
3
0
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
P
3
1
,
P
3
2
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
P
3
3
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
P
3
4
,
P
3
5
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
P
3
6
,
P
3
7
p
u
l
l
-
u
p
c
o
n
t
r
o
l
b
i
t
b
7
b
0
0
:
P
u
l
l
-
u
p
O
f
f
1
:
P
u
l
l
-
u
p
O
n
N
o
t
e
:
P
i
n
s
s
e
t
t
o
o
u
t
p
u
t
p
o
r
t
s
a
r
e
d
i
s
c
o
n
n
e
c
t
e
d
f
r
o
m
p
u
l
l
-
u
p
c
o
n
t
r
o
l
.
P
o
r
t
P
0
P
3
d
r
i
v
e
c
a
p
a
c
i
t
y
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
D
C
C
R
:
a
d
d
r
e
s
s
0
0
1
5
1
6
,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
0
1
6
)
P
o
r
t
P
0
0
d
r
i
v
e
c
a
p
a
c
i
t
y
b
i
t
P
o
r
t
s
P
0
1
,
P
0
2
d
r
i
v
e
c
a
p
a
c
i
t
y
b
i
t
P
o
r
t
s
P
0
3
–P
0
7
d
r
i
v
e
c
a
p
a
c
i
t
y
b
i
t
P
o
r
t
P
3
0
d
r
i
v
e
c
a
p
a
c
i
t
y
b
i
t
P
o
r
t
s
P
3
1,
P
3
2
d
r
i
v
e
c
a
p
a
c
i
t
y
b
i
t
P
o
r
t
P
3
3
d
r
i
v
e
c
a
p
a
c
i
t
y
b
i
t
P
o
r
t
s
P
3
4
,
P
3
5
d
r
i
v
e
c
a
p
a
c
i
t
y
b
i
t
P
o
r
t
s
P
3
6
,
P
3
7
d
r
i
v
e
c
a
p
a
c
i
t
y
b
i
t
b
7
b
0
0
:
L
o
w
1
:
H
i
g
h
N
o
t
e
:
N
u
m
b
e
r
o
f
L
E
D
d
r
i
v
e
p
o
r
t
(
d
r
i
v
e
c
a
p
a
c
i
t
y
i
s
H
I
G
H
)
i
s
8
-
p
o
r
t
.
Fig. 17 Structure of port P0P3 drive capacity control register