LTE-A Module Series
EM160R-GL_Hardware_Design 35 / 73
3.7. PCIe Interface
The module provides one integrated PCIe interface, featuring as follows:
⚫
PCI Express Base Specification Revision 4.0, Version 1.1
⚫
Data rate up to 5 Gbps per lane
Table 13: Pin Definition of PCIe Interface
Pin No. Pin Name
I/O
Description
Comment
55
PCIE_REFCLK_P
AIO
PCIe reference clock (+)
Requires differential
impedance of 95 Ω.
53
PCIE_REFCLK_M
AIO
PCIe reference clock (-)
49
PCIE_RX_P
AI
PCIe receive data (+)
Requires differential
impedance of 95 Ω.
47
PCIE_RX_M
AI
PCIe receive data (-)
43
PCIE_TX_P
AO
PCIe transmit data (+)
Requires differential
impedance of 95 Ω.
41
PCIE_TX_M
AO
PCIe transmit data (-)
50
PERST#
DI
PCIe reset input
Active low.
52
CLKREQ#
DO
PCIe clock request
Active low.
