LTE-A Module Series
EM160R-GL_Hardware_Design 27 / 73
Figure 7: Turn-on Timing
Table 8: Description of Turn-on Timing
⚫
Module:
1) If FULL_CARD_POWER_OFF# is driven high at the same time with VCC, the module will be
able to turn on normally.
2) PERST# needs to be driven high over 100 ms after FULL_CARD_POWER_OFF# is driven high.
Then, PCIe interface will be enabled.
⚫
Host:
1) When the FULL_CARD_POWER_OFF# signal is low, please avoid any leakage current entering
the module's DPR pin from the
h
ost.
2) The host should control FULL_CARD_POWER_OFF# and PERST# based on the timing
sequence.
3) If the host fails to control FULL_CARD_POWER_OFF# and PERST# based on the timing
sequence, instability in PCIe interface will be caused.
For the laptop platform, if there are two reset signals to control PERST# pin of the module, and the
following figure is for reference. It is recommended that AUX Reset be pulled up before Global PCIe
Reset is de-asserted.
Index
Min.
Typ.
Max.
Comment
T1
0 ms
50 ms
-
RESET# will be pulled high internally and automatically when
the host doesn’t pull high RESET#.
If the host pulls low RESET#, module will be under reset state.
T2
0 ms
-
-
The module is waiting for turning on.
T3
0 ms
-
-
⚫
ANT_CONFIG is used for the antenna configuration
High/Floating: 2 antennas (high by default);
Low: 4 antennas.
⚫
Assert ANT_CONFIG before de-asserting PERST#.
⚫
If ANT_CONFIG is not used, T3 could be ignored.
T4
100 ms
-
-
De-assert PERST# 100 ms after de-asserting
FULL_CARD_POWER_OFF#.
T5
1
00 μs
-
-
The period during which PCIE_REFCLK_P/M is stable before
PERST# is de-asserted.
NOTE
