Quectel EM160R-GL, Проектирование аппаратного обеспечения, Страница: 31 / 86

LTE-A Module Series
EM160R-GL_Hardware_Design 30 / 73
VCC(H)
FULL_CARD_
POWER_OFF#
Module Status
RESET#
1.8 V
3.7 V
T4
T2
T3
Active Booting Resetting
V
IH
≥ 1.19 V
CLKREQ#
PERST#
T5
T6
T1
PCIE_REFCLK
Execute AT+CFUN=0 ,
and the module responds OK
Figure 11: Timing of Resetting the Module
Table 11: Description of Reset Timing
⚫
Module:
1) When RESET# is kept at low level for 250 ms or more, the module will reset stably.
2) If PERST# is not pulled down before RESET#, instability in PCIe will be caused. If PERST# is
not pulled high after reset, a system pause will be caused.
⚫
Host:
1) VCC of the system should supply power continuously and FULL_CARD_POWER_OFF# should
be kept at high level.
Index Min. Typ. Max. Comment
T1 15 ms - -
The period from the host PERST# asserting to the its
RESET# asserting.
T2 0 ms 100 ms -
The period from the host RESET# asserting to its
FULL_CARD_POWER_OFF# asserting.
T3 250 ms - -
RESET# should be pulled down for at least 250 ms. An
asserting time less than 250 ms is unreliable.
T4 0 ms - -
The period from the host RESET# releasing to its
FULL_CARD_POWER_OFF# releasing.
T5 100 ms - -
De-assert PERST# 100 ms after de-asserting
FULL_CARD_POWER_OFF#.
T6 1
00 μs -
-
The period during which PCIE_REFCLK_P/M is stable
before PERST# is de-asserted.
NOTE