Quectel 5G Module Series, Проектирование аппаратного обеспечения

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5G Module Series
RM500Q-GL Hardware Design
RM500Q-GL_Hardware_Design 75 / 85
6.3. Digital I/O Characteristic
Table 41: Logic Levels of Digital I/O (1.8 V)
Table 42: (U)SIM 1.8 V I/O Requirements
WCDMA B1 CH10700 @ 23 dBm 560 mA
WCDMA B2 CH9800 @ 23 dBm 570 mA
WCDMA voice
call
WCDMA B3 CH1338 @ 23 dBm 600 mA
WCDMA B4 CH1638 @ 23 dBm 570 mA
WCDMA B5 CH4408 @ 23 dBm 410 mA
WCDMA B6 CH4175 @ 23 dBm TBD mA
WCDMA B8 CH3012 @ 23 dBm 420 mA
WCDMA B19 CH338 @ 23 dBm 440 mA
Parameter Description Min. Max. Unit
V
IH
Input high voltage 1.65 2.1 V
V
IL
Input low voltage -0.3 0.54 V
V
OH
Output high voltage 1.3 1.8 V
V
OL
Output low voltage 0 0.4 V
Parameter Description Min. Max. Unit
USIM_VDD Power supply 1.65 1.95 V
V
IH
Input high voltage 0.7 × USIM_VDD US 0.3 V
V
IL
Input low voltage -0.3 0.2 × USIM_VDD V
V
OH
Output high voltage 0.8 × USIM_VDD USIM_VDD V
V
OL
Output low voltage 0 0.4 V