5G Module Series
RM500Q-GL Hardware Design
RM500Q-GL_Hardware_Design 17 / 85
2.3. Evaluation Board
To help you develop applications conveniently with RM500Q-GL, Quectel supplies an evaluation board
(PCIe Card EVB), a USB to RS-232 converter cable, a USB type-B cable, antennas and other peripherals
to control or test the module. For more details, see
document [3]
.
2.4. Functional Diagram
The following figure shows the functional diagram of RM500Q-GL.
⚫
Power management
⚫
Baseband
⚫
LPDDR4X SDRAM + NAND Flash
⚫
Radio frequency
⚫
M.2 Key-B interface
ANT0
ANT3
ANT2_GNSSL1
38.4MHz XO
Qlink
Control
Tx
PRx
DRx
P
C
I
E
x
p
re
s
s
M
.2
K
e
y
-B
I
n
te
rf
a
c
e
FULL_CARD_POWER_OFF#
W_DISABLE2#
USB 2.0 & USB 3.1
(U)SIM1
WWAN_LED#
WAKE_ON_WAN#
RFFE
W_DISABLE1#
GPIOs
ANT1
PCIe 3.0
×
1
(U)SIM2
GND
RESET#
VCC
S
P
M
I
Clock IC
B
B
_
C
L
K
1
9
.2
M
H
z
R
F
_
C
L
K
3
8
.4
M
H
z
E
B
I1
E
B
I2
3
2
.7
6
8
k
H
z
PMIC
MCP
NAND 4Gb x 8
LPDDR4X 4Gb x 16
Baseband
S
u
b
-6
G
H
z
T
ra
n
s
c
e
iv
e
r
T
x
/R
x
B
lo
c
k
s
E
T
Figure 1: Functional Block Diagram