Qorvo PAC25140, Руководство пользователя

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PAC25140 Users Guide Preview
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Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.
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4 ANALOG REGISTER ACCESS
4.1 Overview
All analog registers in the PAC25140 are accessible through a SOC bus in the device. Unlike
registers in the MCU (SRAM and digital peripheral registers), these analog registers are not
memory mapped.
The block diagram below shows the different system busses that the MCU uses to access the
different system registers.
Figure 4-1 PAC25140 Register Access
SWD
Cortex-M4F
MCU
PACXXXXX
Debug
Port
AHB/APB
Bridge
Analog
Peripherals
GPIOA USARTA
Memory
Controller
JTAG
AHB APB
Other
Digital
Peripherals
DPM
GPIO[A..G]
The PAC25140 contains two register buses: the AHB bus and the APB bus.
The AHB bus allows the MCU and Debug Port access to FLASH and SRAM via the Memory
Controller. To access other digital peripheral connected to the APB bus, there is a bridge from
the AHB to the APB bus so that the MCU or Debug Port can perform memory-mapped register
access to all digital peripherals. Some digital peripherals such as timers are flexibly connected
to IO using the DPM bus.
To access the Analog peripherals, the USARTA SPI peripheral is used to generate read and
write transactions to the Analog registers using the DPM and GPIOA.
4.2 Functional Description
External programming interfaces such as JTAG and SWD or the Arm ® Cortex ® -M4F MCU may
perform memory-mapped accesses to USART A through the AHB and APB busses on the
device.
USART A is a serial communication peripheral that supports a SPI-like protocol that can be
used to communicate to the Analog Peripherals for read and write transactions. The Digital