Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace
95
©1989-2021 Lauterbach GmbH
SYStem.Option HoldReset
Set reset hold time
Set the time that the debugger will drive the reset pin LOW, e.g. at
. The time must be longer
than the BIST takes to complete. If called without parameter, the default reset hold time is used. The default
reset hold time is 100ms for processors that require a BIST delay, else 100us.
SYStem.Option ICFLUSH
Invalidate instruction cache before go and step
Only for cores with dedicated instruction cache (not for unified cache of e200z6 cores).
Default: ON.
Invalidates the instruction cache before starting the target program (Step or Go). If this option is disabled, the
debugger will update Memory and instruction cache for program memory downloads, modifications and
breakpoints. Disabling this option might cause performance decrease on memory accesses.
SYStem.Option ICREAD
Read from instruction cache
Default: OFF:
If enabled,
window and
window for access class P: (program memory) display the
memory values from the instruction/unified cache if valid. If the data is not available in cache, the physical
memory will be displayed.
Format:
SYStem.Option HoldReset
[
<time>
]
<time>
:
1us
…
10s
Format:
SYStem.Option ICFLUSH
[
ON
|
OFF
]
Format:
SYStem.Option ICREAD
[
ON
|
OFF
]
RESET pin
hold time wait time
CPU State
RESET/BIST
RESET
DEBUG_HALT
