Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace
90
©1989-2021 Lauterbach GmbH
Command Reference: SYStem.Option Commands
SYStem.Option BISTRUN
Debug with BIST enabled
MPC5777C only. By default (OFF), the processor will disable BIST if it detects that a debugger is connected
while reset is asserted.
If set to ON, the debugger will connect to the processor only after reset is released. This mode impacts the
debugger’s ability to debug and trace the processor from reset and through power cycles.
SYStem.Option CoreStandBy
On-the-fly breakpoint and trace setup
On multi-core processors, only one of the cores starts to execute code right after reset. The other cores
remain in reset or disabled state. In this state it is not possible to set breakpoints or configure the core for
tracing. This option works around this limitation and makes breakpoints and tracing available on these cores.
SYStem.Option DCFREEZE
Data cache state frozen while core halted
Default: ON. This command configures how the debugger will maintain cache coherence for the debugger’s
memory accesses while the core is halted in debug mode. The setting has no impact on the run-time
memory access.
Format:
SYStem.Option BISTRUN
[
ON
|
OFF
]
Format:
SYStem.Option CoreStandBy
[
ON
|
OFF
]
NOTE:
This option is not required for MPC5676R when operated in SMP mode or when
and
are set to
ON
in
AMP debugging mode.
Format:
SYStem.Option DCFREEZE
[
ON
|
OFF
]
