Qorivva MPC5 Series, Руководство пользователя

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Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 118
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Command Reference: BenchMarkCounter
The BenchMarkCounter features are based on the core’s performance monitor, accessed through the
performance monitor registers (PMR).
TRACE32 displays the benchmark counter results in the BMC.state window:
For information about architecture-independent BMC commands, refer to “BMC” (general_ref_b.pdf).
For information about architecture-specific BMC commands, see command descriptions below.
BMC.<counter>.ATOB Enable event triggered counter start and stop
Enables event triggered counter start/stop. The events are defines using ALPHA and BETA breakpoints set
with
Break.Set . Every time the Alpha breakpoint condition triggers, the counter is started. The counter stops
when the Beta breakpoint condition is triggered.
NOTE:
• These cores do not implement PMRs:
e200z0, e200z1, e200z3
e200z4d
(MPC5643L, SPC56EL, MPC5645S, MPC564xC, SPC56xC)
e200z448 (MPC5644A, SPC564A)
e200z6 and e200z750 .
• These cores only provide PMR access while the core is halted:
e200z759, e200z760 .
• For a list and description of events that can be assigned to
BMC.<counter>.EVENT <event> , please see the Freescale e200z core
reference manuals.
• In addition to the core defined events, TRACE32 provides events
ALPHA...ECHO to count watchpoints set with
Break.Set .
Format: BMC. <counter> .ATOB [ ON | OFF ]